Seung-Min Lee

High Density and Low Power Beam Steering Opto-ULSI Processor for IIPS

This paper presents an optimum phase design implementing a 256 phase beam steering (BS) Opto-ULSI processor (OUP) for multi-function capable optical networks. The world smallest 9um × 9um optical mirror cell to develop an initial 8 phase Opto-ULSI processor that implements a 256-phase BS OUP for integrated intelligent photonic system (IIPS) is to proposed as a target of high density (12mm × 12mm for 1024 × 1024 array) and low power (100mW @1.8v and 50MHz), introducing a novel concept of gray coded switching activity and NAND-NOR combined decoder

A novel design of beam steering n-phase OPTO-ULSI processor for IIPS

This project investigates an optimum phase design implementing a 256 phase Opto-ULSI processor for multifunction capable optical networks. The design of an 8 phase processor is already in construction and will provide the initial base for experimentation and characterization. The challenge is to be able to compensate for the non-linearity of the liquid crystal, find an optimum phase, and implement a larger scale Opto-ULSI processor. This research is oriented around the initial development of an 8 phase Opto-ULSI processor that implements a Beam Steering (BS) Opto-ULSI processor (OUP) for integrated intelligent photonic system (IIPS), while investigating the optimal phase characteristics and developing compensation for the non-linearity of liquid crystal.

Hardware cost-effective and low-power SoC design of DCT-based noise generation system

Noise generation systems are used to generate noise signals with specified characteristics. In recent study, noise generation system using DCT outperforms the conventional noise generation system when a noise model requires complicated PSD (Power Spectral Density) specifications. In this paper, high density and low power structures of non-DCT block in DCT-based noise generation system are proposed. Simulation results show that the high density structure results in area reduction by 61 ~ 64% and the low power structure achieves power reduction by 88 ~ 89%.

Image capture using integrated 3D SoftChip technology

Mobile multimedia communication has rapidly become a significant area of research and development. The processing requirements for the capture, conversion, compression, decompression, enhancement, display, etc. of high quality multimedia content places heavy demands even on current ULSI (ultra large scale integration) systems, particularly for mobile applications where area and power are primary considerations. The system presented is designed as a vertically integrated (3D) system comprising two distinct layers bonded together using indium bump technology. The top layer is a CMOS imaging array containing analog-to-digital converters, and a buffer memory. The bottom layer takes the form of a configurable array processor (CAP), a highly parallel array of soft programmable processors capable of carrying out complex processing tasks directly on data stored in the top plane. Until recently, the dominant format of data in imaging devices has been analog. The analog photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. In the proposed system, an array of analog-to-digital converters is distributed, so that a one-bit cell is associated with one sensor. The analog-to-digital converters are algorithmic current-mode converters. Eight such cells are cascaded to form an 8-bit converter. Additionally, each photosensor is equipped with a current memory cell, and multiple conversions are performed with scaled values of the photocurrent for colour processing.