Seung-Tak Ryu

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting

This paper presents transformer-based self-starting boost converter architecture with low-power maximum power point tracking (MPPT) control for low-voltage thermoelectric generator applications. The minimum working voltage of the proposed boost converter is 40 mV with oscillation through a positive feedback loop formed by a native MOS and transformer. The oscillation autonomously starts up by thermal noise and VOUT is charged up to 1.2 V by the oscillation so that the control block can operate. After that, the transformer for start-up is reused as an inductor, and the normal boost converter mode is enabled for better energy transfer efficiency. An improved MPPT sensing method is also proposed to simplify the circuit. The prototype chip is implemented in a 0.13-μm CMOS process. It operates with an input voltage range of 40 mV to 300 mV and provides a maximum output power of 2.7 mW with a maximum efficiency of 61% at an output voltage of 2 V.

A 550-

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances the conversion speed by 37%. A prototype ADC was implemented in a CMOS 0.13-μm technology. The chip consumes 550 μW and achieves a 50.6-dB SNDR at 40 MS/s under a 1.2-V supply. The figure-of-merit (FOM) is 50 fJ/conversion-step.

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Capacitive touch-screen panels (TSPs) are widely used in recent high-end mobile products on the basis of their high quality of touch features, as well as superior visibility and durability [1-5]. Capacitive TSPs can be classified into self-capacitance [1,2] or mutual-capacitance [3-5] types, according to the sensing mechanism. Compared with the self-capacitance types, which offer low cost and high scan frequency from the simple line-sensing scheme, the mutual-capacitance types, which read out all sensor pixels, are presently widely preferred due to their multi-touch capabilities. However, the reduced sensing time for each sensor makes it difficult to achieve a high signal-to-noise ratio (SNR). Therefore, good noise performance in the analog front-end of the touch controller is essential for mutual-capacitance type TSPs.

10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction

A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic comparators by half. The reduced number of comparators lowers power consumption, load capacitance to the T/H circuit, and the overhead of comparator calibration. The measured peak INL and DNL after comparator calibration are 0.74 and 0.49 LSB, respectively. The measured SNDR and SFDR are 31.2 and 38.3 dB, respectively, with a 2.02-GHz input at 4.1-GS/s operation while consuming 76 mW of total power. This ADC achieves a figure of merit of 0.625 pJ/conversion-step at 4.1 GS/s.

A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels

The rapidly developing electronics industry is producing miniaturized electronic devices with flexible, portable and wearable characteristics, requiring high-performance miniature energy storage devices with flexible and light weight properties. Herein, we have successfully fabricated highly porous, binder free three-dimensional flower-like NiCo2O4/Ni nanostructures on Ni-wire as a fiber electrode for high-performance flexible fiber supercapacitors. Such a unique structure exhibited remarkable electrochemical performance with high capacitance (29.7 F cm−3 at 2.5 mA), excellent rate capability (97.5% retention at 20 mA), and super cycling stability (80% retention, even after 5000 cycles). The remarkable electrochemical performance is attributed to the large active area in the 3D porous architecture and direct contact between the active materials and 3D-Ni current collectors, which facilitate easy ionic/electronic transport. The symmetric fiber supercapacitor showed a gravimetric energy density of 2.18 W h kg−1 (0.21 mW h cm−3) and a power density of 21.6 W kg−1 (2.1 mW cm−3) with good flexibility and cycling performance, signifying potential applications in high-performance flexible energy storage devices. Further, performance in a self-powered system was demonstrated by charging these wire type NiCo2O4/Ni supercapacitors by serially wound DSSCs to drive commercial LEDs. These results suggest that the fabricated device has excellent potential as a power source for flexible, portable and wearable applications as well as self-powered systems.

A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS

With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures, power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures made contributions in realizing high-speed single-channel ADCs with high resolution by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic and DACs for 2b/cycle implementations have been of trivial concern for low resolution ADCs. However, as resolution increases, the complexity of such circuits becomes considerable, with power taking up a big share of the total. In this paper, a multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in the work of Kong et al. (2013), is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions. A low-power 2.6b/cycle-based SAR ADC architecture is presented as a proof of concept.

Realization of high performance flexible wire supercapacitors based on 3-dimensional NiCo2O4/Ni fibers

By taking advantage of the merits of the low power consumption and hardware simplicity of SAR ADCs, 2b/cycle conversion structures in SAR ADCs have been actively studied in recent years for enhanced conversion rates and excellent FoM [1-3]. However, many error sources in the 2b/cycle SAR ADCs, such as mismatches between DACs and comparators, and the signal-dependent errors from comparators, namely kickback noise and offset, make it difficult to achieve high resolution. To date, pure 2b/cycle structures operating above hundreds of MS/s have shown a somewhat limited resolution with an ENOB lower than 7 at Nyquist rates [1,2]. As a derivation of the structure, a sub-ADC could be implemented using the 2b/cycle SAR ADC structure for high resolution as in [4], at the cost of increased circuit complexity and static current flow. In this work, we present a resolution-enhancing design technique for 2b/cycle SAR ADCs with negligible hardware overhead, while relieving the requirements for the aforementioned errors: Reconfiguration from a 2b/cycle structure to a normal 1b/cycle SAR ADC with error-correction capability achieves an 8.6 ENOB from a 9b ADC.

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique

In this paper, a compensation technique for realizing a precise decibel-linear CMOS programmable gain amplifier (PGA) is described. The proposed PGA, employing an auxiliary pair, not only retains a constant current density but also offers a gain-independent bandwidth (BW). For verification, a compact PGA (0.1 mm2) is fabricated using a 0.13-μm CMOS process and measured. The measured gain control range is from -16 to + 32 dB with 6-dB steps, while the error deviation of the gain is less than 0.35 dB. A constant 3-dB BW of 60 MHz and an input P1dB of -35 to -5 dBm are obtained, while dissipating a lower power of 1.2 mW under a 1-V supply.

An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement

A compact low-power on-chip power-on reset circuit with a brown-out detection capability is presented. With a pico-farad-order on-chip MOS capacitor, a long reset time is achieved. A prototype design implemented in a 0.18-μm CMOS process provides a reset signal with duration of hundreds of milliseconds. The embedded brown-out detection circuit can detect the event, as long as the brown-out duration is longer than the millisecond range. The chip consumes only 1 μA under a 1.8-V supply and occupies a 120 μm × 100 μm active area.

A Precise Decibel-Linear Programmable Gain Amplifier Using a Constant Current-Density Function

A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different designated functions, SIG-DAC and REF-DAC, are implemented to make the structure compact and to eliminate the sampling skew issue. Use of a nonbinary decision scheme with decision redundancies not only increases the ADC speed with a relaxed DAC settling requirement but also makes the performance robust to reference fluctuations and comparator offset variations. The proposed dynamic register and direct DAC control scheme enhance the conversion speed by minimizing logic delay in the SAR decision loop. The proposed comparator-error detection with digital error correction scheme enhances high-speed ADC performance. A prototype 7b ADC fabricated in a 45 nm CMOS process operates at a sampling rate of 1 GS/s under a 1.25 V supply while achieving a peak SNDR of 41.6 dB and maintaining an ENOB higher than 6 up to 1.3 GHz signal frequency. The FoM under a 1.25 V supply is an 80 fJ/conversion-step with a power consumption of 7.2 mW.