Jun-Hyeok Yang

A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels

Capacitive touch-screen panels (TSPs) are widely used in recent high-end mobile products on the basis of their high quality of touch features, as well as superior visibility and durability [1-5]. Capacitive TSPs can be classified into self-capacitance [1,2] or mutual-capacitance [3-5] types, according to the sensing mechanism. Compared with the self-capacitance types, which offer low cost and high scan frequency from the simple line-sensing scheme, the mutual-capacitance types, which read out all sensor pixels, are presently widely preferred due to their multi-touch capabilities. However, the reduced sensing time for each sensor makes it difficult to achieve a high signal-to-noise ratio (SNR). Therefore, good noise performance in the analog front-end of the touch controller is essential for mutual-capacitance type TSPs.

A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs

This paper presents a 10-bit column driver IC for active-matrix LCDs, with a proposed iterative charge-sharing based (ICSB) capacitor-string that interpolates two output voltages from a resistor-string DAC. Iterative mode change between a capacitive voltage division mode and a charge sharing mode in the ICSB capacitor-string interpolation suppresses the effect of mismatches between capacitors and that of parasitic capacitances; thus, a highly linear capacitor sub-DAC is realized. In addition, the area-sharing layout technique, which stacks the interpolation capacitor-string on top of the R-DAC area, reduces the driver channel size and extends the bit resolution of the gamma-corrected nonlinear main R-DAC. Consequently, the proposed ICSB capacitor-string interpolation scheme provides highly uniform channel performance by passively dividing the coarse voltages from the global resistor-string DAC with high area efficiency, and more effective bit resolution for nonlinear gamma correction. The prototype column driver IC was implemented using a 0.11-μm CMOS process. The area occupation of the DAC and buffer amplifier per channel is only 188 × 15 μm2, and the static power consumption is 0.9 μA/channel with no additional static power dissipation for the interpolation. The measured maximum DNL and INL are 0.25 LSB and 0.43 LSB, respectively. The measured maximum inter-channel DVO is 5.6 mV. The proposed chip achieves state-of-the-art performance in terms of chip size and channel-to-channel uniformity.

An Asynchronous Sampling-Based 128

This paper presents a direct photon-counting X-ray image detector with a HgI2 photoconductor for high-quality medical imaging applications. The proposed sampling-based charge preamplifier with asynchronous self-reset enables a pixel to detect single X-ray photon energy with higher sensitivity and faster processing rate. The use of the correlated double sampling enabled by the sampling-based architecture also reduces flicker noise and contributes to the achievement of high pixel-to-pixel uniformity. Discrimination of the energy level of the detected X-rays is performed by the proposed compact in-pixel ADC with low power consumption. Three 15-bit counters in each pixel count up energy-discriminated photons for the reconstruction of multispectral X-ray images. A 128 × 128 X-ray image detector with a pixel size of 60 × 60 μm2 is implemented and measured using a 0.13-μm/0.35-μm standard CMOS process. It discriminates 3 energy levels of photon energy with a gain of 107 mV/ke- and a static power consumption of 4.6 μW/pixel. The measured equivalent noise charge (ENC) and minimum detectable energy level of the detector pixel are 68 e- rms and 290 e-, respectively. The measured maximum threshold dispersion in the pixel array is 164 e- rms without any calibration. The functionality of our chip is also successfully demonstrated using real X-ray images.

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The critical issues in charge-based touch screen panels for large size display are noise and speed. To solve these, this paper introduces a two-point relative sensing based ‘Delta-Integration’ scheme. It eliminates local noise and increases a readout difference between the touched and non-touched area. As a result, it can replace a high-resolution ADC with a comparator and counter. In addition, the single-bit conversion of Δ-integration method and the proposed wide-bandwidth charge amplifier solve a speed issue of a large display. The prototype chip is implemented in a 0.35-µm CMOS technology.

128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution

Computer-aided design (CAD) models have errors that originate from data loss during the data conversion process or the technical weakness of the neutral format. Error recovery requires an increase in lead-time and additional expenses for product development. The serious problem is that errors in a CAD model are not found until after downstream development processes. In this paper, we propose a method to identify CAD model errors that are contained in a neutral format. Considering different topological and geometrical characteristics in the exchange of product model data (STEP) and initial graphics exchange specification (IGES) formats, our method includes a verification process to check a CAD model error step by step without wasting resources. To test the idea, we have implemented a verification system that checks topological and geometrical errors of 19 items in the STEP format and 12 items in the IGES format.

A novel readout IC with high noise immunity for charge-based touch screen panels

To achieve high image quality in mobile active-matrix LCDs, higher DAC resolution and good channel-to-channel uniformity are required in column-driver ICs. In conventional column-driver ICs, the resistor-DAC (R-DAC) architecture has been generally used due to its uniform characteristic, because each R-DAC in driver channels shares a common resistor string for gamma reference-voltage generation. Furthermore, nonlinear gamma correction can be easily implemented using a nonlinear resistor-string that has an inverse transfer curve to the liquid crystal (LC) response. However, the increase in color depth for LCDs results in a large chip-size overhead, thus disclosing the limitation of the R-DAC architecture. To overcome this issue, several hybrid DAC architectures composed of a main 6b R-DAC and a 4b sub-DAC with various interpolation schemes have been reported [1-5]. Their linear interpolation schemes reduce the driver channel size. Meanwhile, their linear 4b interpolation leads to the loss of effective bit resolution for nonlinear gamma correction. In addition, the inevitable mismatch between respective sub-DACs has a significant influence on the channel-to-channel uniform performance of a column-driver IC. In this paper, we present a 10b column-driver IC with a mismatch-free switched-capacitor (SC) interpolation scheme for mobile AMLCDs. The proposed mismatch-free interpolation scheme provides further reduction of the driver size, good linearity, highly uniform channel performance, and more effective bit resolution.

A method for verification of computer-aided design model errors

An area-efficient 9-bit digital-to-analog converter (DAC) for application in current-mode active-matrix organic light-emitting diode mobile display drivers is presented. To reduce the chip size, the proposed DAC is realized with a novel switched-current architecture, which periodically receives digital bits one by one in series to perform single bit conversion. A high-performance current-mode S/H circuit is also suggested in order to increase the sampling speed and linearity of the DAC. The prototype 9-bit DAC occupies only 0.014 mm2 per channel in a 0.35- μm CMOS process and achieves a 100-kS/s conversion rate at a static current of 10 μA under a 3.3-V supply. The measured maximum integral and differential nonlinearities are 1.6 and 0.8 LSB, respectively. Measured maximum interchannel current output deviations in the best and the worst chips are 15 and 35 nA, respectively.

A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs

This paper proposes a 10 bit linear interpolation digital-to-analog converter (DAC) with area efficiency and a high resolution for an AMLCD drive. Because this proposed structure implements a 1 bit interpolation circuit with a control block for a loop gain ratio, it shows a wide voltage range of interpolation as well as superior linearity. The proposed circuit is fabricated with Samsung 90nm CMOS 1.5V / 5V technology. The power dissipation is 7uW/channel, and the chip area of the 10 bit piecewise linear DAC is only 91% of the area of a conventional 8 bit resistor DAC. The INL and DNL properties are +0.8LSB/−0.2LSB and +0.23LSB/-0.23LSB, respectively. The maximum interchannel DVO is 10mV without the application of any offset cancellation techniques.

A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers

Active-Matrix Organic LED (AMOLED) technology has attracted a considerable amount of attention as a very desirable display due to superior characteristics such as its wide viewing angle, fast response, thinness, and low power consumption. Among various driving techniques for AMOLED displays, the current-driving scheme deals well with the issues of spatial and temporal variation of the TFT as well as IR drops in the pixel circuits [1]. Several previous works have successfully demonstrated this [2–3]. Figure 17.9.1 shows a block diagram of an AMOLED display system adopting a current-driving scheme. The digital-to-analog converter (DAC) plays a key role in the column driver by reconstructing the analog signal for pixel-driving from digital data. Considering that the number of columns of pixels continues to increase, even in mobile-oriented displays, the chip area occupied by the DAC should be greatly reduced. Furthermore, as widescreen displays such as WXGA are coming into wider use, it is necessary for column drivers for these displays to have a narrow channel pitch.

A 10 bit piecewise linear cascade interpolation dac with loop gain ratio control

A 10-bit serial integration-type DAC architecture based on discrete-time integrator using switched-capacitor structure is proposed for AMLCD column drivers in this paper. This proposed serial DAC architecture can dramatically reduces its size by minimizing the size of capacitors used for integration using a simple capacitor swapping algorithm per frame. The design of the proposed DAC was dedicated to mobile application and has been fabricated in 0.35μm 3.3V CMOS process.