Seungbum Lim

A Technology Overview of the PowerChip Development Program

The PowerChip research program is developing technologies to radically improve the size, integration, and performance of power electronics operating at up to grid-scale voltages (e.g., up to 200V) and low-to-moderate power levels (e.g., up to 50W) and demonstrating the technologies in a high-efficiency light-emitting diode driver, as an example application. This paper presents an overview of the program and of the progress toward meeting the program goals. Key program aspects and progress in advanced nitride power devices and device reliability, integrated high-frequency magnetics and magnetic materials, and high-frequency converter architectures are summarized.

Two-Stage Power Conversion Architecture Suitable for Wide Range Input Voltage

This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches.

Measurements and Performance Factor Comparisons of Magnetic Materials at High Frequency

The design of power magnetic components for operation at high frequency (HF, 3-30 MHz) has been hindered by a lack of magnetic material performance data and by the limited design theory in that frequency range. To address these deficiencies, we have measured and present core loss data for a variety of commercially available magnetic materials in the HF range. In addition, we extend the theory of performance factor for appropriate use in the HF design. Since magnetic materials suitable for HF applications tend to have low permeability, we also consider the impact of low permeability on design. We conclude that, with appropriate material selection and design, increased frequencies can continue to yield improved power density well into the HF regime.

Two-stage power conversion architecture for an LED driver circuit

This paper presents a merged-two-stage circuit topology suitable for efficient LED drivers operating from either wide-range dc input voltage or ac line voltage. This two-stage topology is based on a soft-charged switched-capacitor pre-regulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect scale current control are used to maintain high efficiency, high power density, and high power factor. Two implementations of the proposed architecture are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 85-95% efficiency at 20 W power across 25-200 V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4 W average power.

New AC–DC Power Factor Correction Architecture Suitable for High-Frequency Operation

This paper presents a novel ac-dc power factor correction (PFC) power conversion architecture for a single-phase grid interface. The proposed architecture has significant advantages for achieving high efficiency, good power factor, and converter miniaturization, especially in low-to-medium power applications. The architecture enables twice-line-frequency energy to be buffered at high voltage with a large voltage swing, enabling reduction in the energy buffer capacitor size and the elimination of electrolytic capacitors. While this architecture can be beneficial with a variety of converter topologies, it is especially suited for the system miniaturization by enabling designs that operate at high frequency (HF, 3-30 MHz). Moreover, we introduce circuit implementations that provide efficient operation in this range. The proposed approach is demonstrated for an LED driver converter operating at a (variable) HF switching frequency (3-10 MHz) from 120 Vac, and supplying a 35 Vdc output at up to 30 W. The prototype converter achieves high efficiency (92%) and power factor (0.89), and maintains a good performance over a wide load range. Owing to the architecture and HF operation, the prototype achieves a high “box” power density of 50 W/in3 (“displacement” power density of 130 W/in3), with miniaturized inductors, ceramic energy buffer capacitors, and a small-volume EMI filter.

Power conversion architecture for grid interface at high switching frequency

This paper presents a new power conversion architecture for single-phase grid interface. The proposed architecture is suitable for realizing miniaturized ac-dc converters operating at high frequencies (HF, above 3 MHz) and high power factor, without the need for electrolytic capacitors. It comprises of a line-frequency rectifier, a stack of capacitors, a set of regulating converters, and a power combining converter (or set of power combining converters). The regulating converters have inputs connected to capacitors on the capacitor stack, and provide regulated outputs while also achieving high power factor, with twice-line-frequency energy buffered on the capacitor stack. The power combining converter combines power from the individual regulated outputs to a single output, and may also provide isolation. While this architecture can be utilized with a variety of circuit topologies, it is especially suited for systems operating at HF (above 3 MHz), and we introduce circuit implementations that enable efficient operation in this range. The proposed approach is demonstrated for an LED driver operating from 120 Vac, and supplying a 35 V, 30 W output. The prototype converter operates at a (variable) switching frequency of 5-10 MHz and an efficiency of > 93%. The converter achieves a displacement power density of 130 W/in3, while providing a 0.89 power factor, without the use of electrolytic capacitors.

A multi-mode multi-band CMOS direct-conversion mobile-TV tuner for DVB-H/T and T-DMB/DAB applications

A fully integrated direct-conversion mobile-TV tuner for DVB-H/T and T-DMB/DAB applications was fabricated using 0.18 um CMOS process. This tuner has the good SNR and immunity performance over wide dynamic range for multi-band and multi-mode applications with the automatic gain control and calibration schemes. The power consumption is 127 mW for VHF and UHF, and 135 mW for L-band at 1.8 V supply voltage.

Capacitively-aided switching technique for high-frequency isolated bus converters

This paper presents a new capacitively-aided zero voltage switching (ZVS) technique for isolated bus converters. The proposed technique helps to achieve ZVS conditions for both inverter and rectifier switches with the aid of magnetizing current of the transformer and capacitors interconnecting primary and secondary side switching nodes. With the proposed topology, the ZVS conditions for inverter and rectifier switches occur at the same time, and (ideally) maintain constant required dead time independent of the load level of the converter. These features are particularly advantageous especially for designs operating at high frequencies where timing control becomes critical. The proposed approach is demonstrated in a 1.4 MHz prototype converter which operates from 36 Vdc and supplies a 12 Vdc output load (i.e., fixed input voltage and fixed voltage transformation ratio, 3 : 1 ) at a 36 W rating. Experimental results show ZVS operation of all devices independent of the load level, and the prototype converter achieves 94% peak efficiency with 300 W/ in3 power density.

A 1.2V 57mW mobile ISDB-T SoC in 90nm CMOS

This paper presents a 1.2 V 57 mW SoC using a 90 nm CMOS process in mobile ISDB-T application. This achieves −98.5 dBm sensitivity at QPSK, CR = −2/3 with 2.5 dB NF of RF tuner block and 5.6 dB C/N of OFDM block at UHF-band. To integrate RF tuner and OFDM in a small single die, a wideband single LC-VCO operating from 1.8 GHz to 3.3 GHz is proposed and OFDM is designed by hard-wired logic.

GaNFET compact model for linking device physics, high voltage circuit design and technology optimization

This work is the first demonstration of a physics-based GaN HEMT compact model that is calibrated and verified all the way from individual device-to a HV-buck converter circuit, along with an illustration of use in technology optimization. GaN HEMT based high voltage (HV) switching converters are gaining foothold in the medium voltage (<;1000 V) power conversion applications. The superior breakdown voltage, operating frequency, and high temperature performance of GaN HEMTs enable improved conversion efficiency and smaller footprint of the converters [1]. In order to design such high voltage GaN circuits, the device compact model must accurately describe static and dynamic switching behavior to enable designers to gain insight into the impact of the behavioral nuances of the GaN HEMTs on HV circuit performance, such as non-quasi-statics, which is not possible with the available models such as EEHEMT, Curtice, and Angelov models [2]. The model is validated against DC-IV, -CV, and pulsed-IV measurements of fabricated devices and is then verified by comparing measured and simulated signals in a commercial buck converter. Furthermore we demonstrate that our physics-based model can be used as a device design and multi-dimensional optimization tool to estimate device parameters such as field plate (FP) lengths and FP dielectric thicknesses (td) to maximize the switching figure-of-merit (FoM), BV/RonQg.