Sungho Beck

A multi-mode multi-band CMOS direct-conversion mobile-TV tuner for DVB-H/T and T-DMB/DAB applications

A fully integrated direct-conversion mobile-TV tuner for DVB-H/T and T-DMB/DAB applications was fabricated using 0.18 um CMOS process. This tuner has the good SNR and immunity performance over wide dynamic range for multi-band and multi-mode applications with the automatic gain control and calibration schemes. The power consumption is 127 mW for VHF and UHF, and 135 mW for L-band at 1.8 V supply voltage.

A High IIP2 Direct-Conversion Receiver Using Even-Harmonic Reduction Technique for Cellular CDMA/PCS/GPS Applications

A high IIP2 direct-conversion receiver for cellular CDMA/PCS/GPS has been developed in a 0.35 mum SiGe BiCMOS process. This receiver consists of a RF front-end chip and a base-band chip. The RF front-end chip includes three LNAs, three mixer cores with a common output stage, and LO distribution blocks. The base-band chip includes a channel selection filter, an output buffer, and a DC calibration block. To achieve high IIP2 performance, an even-harmonic reduction technique is proposed based on a simplified analysis of second-order intermodulation. A 40-dB improvement of the IIP2 performance is accomplished by this technique, which reduces sensitivity to operating conditions and to output load mismatches. This receiver also attains high IIP3 and a low-noise figure. Measurement results show 71 dBm IIP2, -1.3 dBm IIP3, and 2.4 dB NF for Cellular CDMA; 68 dBm IIP2, - 3.7 dBm IIP3, and 2.9 dB NF for PCS; and 26 dBm IIP2 -30 dBm IIP3, and 2 dB NF for GPS.

A fully-integrated low power direct conversion transmitter with fractional-N PLL using a fast AFC technique for CDMA applications

The paper presents a fully integrated low power direct conversion transmitter IC for CDMA applications. To reduce the power consumption and reduce switching time, a fractional-N frequency synthesizer with an internal VCO is integrated into the transmitter IC and an N-target algorithm is proposed to implement automatic frequency calibration (AFC). Total locking time is approximately 200 /spl mu/s, including 80 /spl mu/s AFC lock time. Total current consumption for -80 dBm, -10 dBm, and 8 dBm output power are 27 mA, 33 mA, and 60 mA, respectively. This chip is housed in a small 5 mm /spl times/ 5 mm 32 pin MLF package.

Analog auto-correlation based receiver architecture for radar systems

Analog signal processing based radar systems enable reduction in total system power consumption, over conventional digital signal processing based radar systems. In this paper, detection performance degradation of a previously proposed system, based on analog cross-correlation, due to time synchronization is addressed and analog auto-correlation based radar architecture is proposed. By adopting the digital radio frequency memory technique, accurate and tunable delays for autocorrelation process are realized. The probability of detection performance degradation of the previously proposed system, due to mismatch, is evaluated by simulations while varying signal to noise ratios and mismatches at the matched filter. The proposed systems probability of detection performance will also be simulated versus varying signal to noise ratios, compared to the results of the previously proposed system and analysis of conditions when the proposed system is more beneficial than the previously proposed system will be made.

Subthreshold current mode matrix determinant computation for analog signal processing

The matrix determinant computation system (MDCS) is developed in subthreshold current-mode for an analog signal processing. By utilizing the translinear loop principle and the novel differential architecture, the MDCS can perform accurate addition, subtraction, and multiplication in analog domain. The system computes a 2-by-2 and 3-by-3 determinant with 91 % accuracy and a 3 kHz input can be handled while consuming 110.05μW. The overall system is fabricated on a 0.18μm CMOS technology and the area is 500μm × 800μm.

A Fully Integrated Low-IF Image Reject Receiver for T-DMB and DAB Applications

This paper describes a fully integrated low-IF image reject receiver for triple-band T-DMB and DAB applications. The receiver features an efficient local oscillator (LO) frequency planning using a wideband low phase noise voltage-controlled oscillator (VCO) for improved low-IF receiver performance. The tuning range of the VCO is measured from 2.65 to 3.95GHz covering all the required frequency bands (Band-II, Band-Ill, and L-Band). The receiver shows a measured noise figure (NF) of under 2dB, thereby achieving a sensitivity of lower than -100dBm with 100mW power consumption. The maximum input signal level of the receiver is lOdBm, resulting in HOdB dynamic range. Total image rejection of over 50dB is achieved. The receiver is fabricated in a 0.25-mum BiCMOS process and packaged in a 5mm x 5mm 32-pin MLF package.

A precise temperature-insensitive and linear-in-dB variable gain amplifier

A fully temperature-compensated linear-in-dB variable gain amplifier (VGA) is presented. The VGA achieves wide dynamic range and precise linear-in-dB control capability using a translinear current amplifier. The compensation technique having current proportional to the squared temperature is proposed. The VGA is implemented with 0.35 /spl mu/m SiGe BiCMOS process. Greater than 90 dB dynamic range while having only /spl plusmn/3 dB gain drift from -30/spl deg/C to 85/spl deg/C temperature range is measured.

A multi-band WCDMA SAW-less receivers with frequency selective feedback loop

For frequency division duplex (FDD) wide band code division multiple access (WCDMA) system, transmit (TX) signal leakage at the receiver input degrades the receiver performance. Previously, to cancel the TX leakage, a frequency selective feedback was proposed, but it had the unpredictable feedback loop characteristic due to the uncertainty of the duplexer impedance. This paper proposes a new method to achieve a predictable feedback loop characteristic. In addition, to achieve the TX leakage cancellation for multi-band, a local oscillator (LO) phase shift technique is also presented. The proposed receiver which was composed of high- and low-band LNAs and mixers, the TX canceller, and the LO shifter was implemented using 0.18-µm CMOS process and is under fabrication. Simulation results met the required specifications which were delivered from the WCDMA specifications.

A 45nm SOI-CMOS PLL with a wideband LC-VCO

A 45nm SOI-CMOS PLL with a wideband LC-VCO is presented. The proposed PLL uses the advantage of SOI technology such as small parasitic capacitance and high Q-factor. The frequency range of the PLL is maximized because of a high maximum-to-minimum capacitance ratio of a capacitor bank. Measurement results show that the VCO generates 4.87-to-9.65GHz frequency signals with 65.8% frequency coverage. Fabricated chip occupies 0.09mm2 of active area and consumes less than 7mA current from single 1.0V supply.

A 1.8dB NF 300mW SiP for 2.6GHz diversity S-DMB application

This paper presents a 1.8V 300mW System-In-Package (SiP) solution in mobile S-DMB application. This achieves a 1.8 dB noise figure at 2.6GHz, while the measured sensitivity is −101 dBm at diversity mode. The SiP is integrated RF tuner, demodulator, SDRAM and other passive components. An internal AGC is integrated for over 100dB dynamic range. The SiP is 196 pins LFBGA and the size is 10 mm × 10 mm × 1.3 mm. The SiP consumes 300mW.