Seungwhun Paik

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches

Pulsed latches, latches driven by a brief clock pulse, offer the same convenience of timing verification and optimization as flip-flop-based circuits, while retaining the advantages of latches over flip-flops. But a pulsed latch that uses a single pulse width has a lower bound on its clock period, limiting its capacity to deal with higher frequencies or operate at lower Vdd. The limitation still exists even when clock skew scheduling is employed, since the amount of skew that can be assigned and realized is practically limited due to process variation. For the first time, we formulate the problem of allocating pulse widths, out of a small discrete number of predefined widths, and scheduling clock skews, within a predefined upper bound on skew, for optimizing pulsed latch-based sequential circuits. We then present an algorithm called PWCS_Optimize (pulse width allocation and clock skew scheduling, PWCS) to solve the problem. The allocated skews are realized through synthesis of local clock trees between pulse generators and latches, and a global clock tree between a clock source and pulse generators. Experiments with 65-nm technology demonstrate that combining a small number of different pulse widths with clock skews of up to 10% of the clock period yield the minimum achievable clock period for many benchmark circuits. The results have an average figure of merit of 0.86, where 1.0 indicates a minimum clock period, and the average reduction in area by 11%. The design flow including PWCS_Optimize, placement and routing, and synthesis of local and global clock trees is presented and assessed with example circuits.

Pulsed-Latch Circuits: A New Dimension in ASIC Design

Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher performance and lower power consumption within a conventional ASIC design environment. This article identifies a design methodology and tools for pulsed-latch ASICs to complement this environment. The authors review potential solutions and provide quantitative results to assess the effectiveness of pulsed-latch circuits.

Pulser gating: a clock gating of pulsed-latch circuits

A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. Given a gate-level netlist with location of latches, we first extract the gating function of each latch; the gating functions are merged to reduce the amount of extra logic while gating probability is not sacrificed too much. We also have to take account of proximity of latches, because a pulser, which is gated by merged gating function, and its latches have to be physically close for safe delivery of pulse. The heuristic algorithm that considers all three factors (similarity of gating functions, literal count to implement gating functions, and proximity of latches) is proposed and assessed in terms of power saving and area using 45-nm technology.

Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits

Pulsed-latches take advantage of both latches in their high performance and flip-flops in their convenience of timing analysis. To minimize the clock period of pulsed-latch-based circuits for a higher performance, a problem of combined retiming and time borrowing is formulated, where the latter is enabled by using a handful of different pulse widths. The problem is first approached by formulating it as an integer linear programming to lay a theoretical foundation. A heuristic approach is proposed, which solves the problem by performing clock skew scheduling for the minimum clock period and gradually converting skew into a combination of retiming and time borrowing. Experiments with 45-nm technology demonstrate that the clock period close to the minimum can be achieved for all benchmark circuits with an average of 1.03× with less use of extra latches compared to the conventional retiming. Categories and Subject Descriptors: B.6.1 [Logic Design]: Design Styles-Sequential circuits; B.7.1 [Integrated Circuits]: Types and Design Styles-VLSI General Terms: Algorithms, Design

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

Pulsed latches, latches driven by a brief clock pulse, offer the convenience of flip-flop-like timing verification and optimization, while retaining superior design parameters of latches over flip-flops. But, pulsed latch-based design using a single pulse width has a limitation in reducing clock period. The limitation still exists even if clock skew scheduling is employed, since the amount of skew that can be assigned is practically limited due to process variations. The problem of allocating pulse width (out of discrete number of predefined widths) and scheduling clock skew (within prescribed upper bound) is formulated, for the first time, for optimizing pulsed latch-based sequential circuits. An allocation algorithm called PWCS_Optimize is proposed to solve the problem. Experiments with 65-nm technology demonstrate that small number of variety of pulse widths (up to 5) combined with clock skews (up to 10% of clock period) yield minimum clock period for many benchmark circuits. The design flow including PWCS_Optimize, placement and routing, and synthesis of local and global clock trees is presented and assessed with example circuits.

Register allocation for high-level synthesis using dual supply voltages

Reducing the power consumption of memory elements is known to be the most influential in minimizing total power consumption, since designs tend to use more memories these days. In this paper, we address a problem of high-level synthesis with the objective of minimizing power consumption of storage using dual-Vdd. Specifically, we propose a complete design framework that starts from dual-Vdd scheduling, dual-Vdd allocation, and controller synthesis down to the final layout. Its main feature is dual-Vdd register allocation, which exploits timing slacks left in the data-path after operation scheduling. In experiments on benchmark designs implemented in 1.08 V (with Vddl of 0.8 V), 65-nm CMOS technology, both switching and leakage power were reduced by 20% on average, respectively, compared to data-path with dual-Vdd applied to functional units alone. Detailed analysis of slack histogram, area, wirelength, and congestion were performed to assess feasibility of the design framework.

Pulsed-latch circuits to push the envelope of ASIC design

The use of the slow and power-consuming flip-flops is one of the factors that cause a large gap between custom and ASIC designs. A pulsed-latch, which is a latch driven by a brief pulse clock, inherits the advantage of latch while allowing us to use a simple timing model similar to that of flip-flop. As a result, it offers the opportunity of higher performance and lower power consumption within the conventional ASIC design environment. We address challenges and problems specific to pulsed-latch ASIC, and review potential solutions. Some quantitative results are provided to assess the effectiveness of pulsed-latch circuits.

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures

Level-sensitive latches are widely used in high-performance custom designs while edge-triggered flip-flops are predominantly used in application-specific integrated circuits. We consider a latch as a basis for storage and address each step of high-level synthesis (HLS), including scheduling, allocation, and control synthesis. While the use of latches provides an opportunity to reduce the latency during the scheduling, the register allocation has to take extra conflicts caused by latch into account, and the control synthesis has to be tailored to support the latch-based data-path. Optimization potentials specific to this HLS are identified and solutions are proposed. Specifically, the register allocation can be improved by refining the operation schedule in a way to reduce the number of edges in a register conflict graph; the latency can be reduced by adjusting the clock duty cycle in a way to generate a tighter schedule. All the steps of HLS and optimization procedures were integrated into a framework called HLS-l. It was tested on benchmark designs implemented in 1.1-V, 45 nm complementary metal-oxide-semiconductor technology. Compared to the conventional HLS, HLS-l was able to reduce the latency by 18.2% on average with 9.2% less area and 16.0% less power consumption. The application of HLS-l to an industrial example is demonstrated through the design of a module extracted from H.264/advanced video coding.

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

A pulsed-latch can be modeled as a fast flip-flop. This allows conventional flip-flop designs to be migrated to pulsed-latch versions by simple replacement to reduce the clocking power. A key step in the migration process is to insert pulsers, which generate clock pulse to drive local latches; the number of pulsers as well as the wirelength of clock routing must be minimized to reduce the clocking power. We formulate a pulser insertion problem to find a set of latch groups where each group shares a pulser and its load constraint is satisfied; both an ILP formulation and a heuristic algorithm are presented to solve the problem. Experimental results of circuits implemented with 32-nm CMOS technology show that the clocking power of pulsed-latch designs obtained by our approach is 5.9% less than that of greedy approach; this is 44.7% less than that of flip-flop designs. We also consider the problem of pulsed-register where a pulser is integrated with multiple latches. A concept of logical distance is explored during our clustering algorithm to minimize the overhead of signal wirelength when converting flip-flops to pulsed-registers. Compared with flip-flop circuits, signal wirelength is increased by 6.3%, which is 1.4% smaller than without considering logical distance, while reducing the clocking power by 24%.

Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements

Zigzag power gating (ZPG) can overcome the long wake-up delay of standard power gating, but its requirement for both nMOS and pMOS current switches, in a zigzag pattern, requires complicated power networks, limiting application to custom designs. We propose a design framework for cell-based semicustom design of ZPG circuits, using a new power network architecture that allows the unmodified conventional logic cells to be combined with custom circuitry such as ZPG flip-flops, input forcing circuits, and current switches. The design flow, from register transfer level description to layout, is described and applied to a 32-b microprocessor design using a 1.2-V 65-nm triple-well bulk CMOS process. The use of a sleep vector in ZPG requires additional switching power when entering standby mode and returning to active mode. The switching power should be minimized so that is does not outweigh the leakage saved by employing ZPG scheme. We formulate the selection of a sleep vector as a multiobjective optimization problem, minimizing both the transition energy and the total wirelength of a design. We solve the problem by employing multiobjective genetic-based algorithm. Experimental results show an average saving of 39% in transition energy and 8% in total wirelength for several benchmark circuits in 65-nm technology.