Donkyu Baek

Power consumption characterization, modeling and estimation of electric vehicles

Rapid electric vehicle (EV) penetration gives a threatening challenge in electric energy generation. An 1,814 kg curb weight full electric vehicle driving 18,129 km/year consumes electricity energy equivalent to 74% of the total residential electricity use per person in the US. This implies that 27% more nationwide electricity generation is needed when 70% of passenger vehicles are replaced with EVs. This paper is the first step toward systematic EV design-time and runtime optimization. We introduce instantaneous power consumption modeling of an EV by the curb weights, speed, acceleration, road slope, passenger and cargo weights, motor capacity, and so on, as a battery discharge model. The model also considers the onboard charger, regenerative braking and so on, as a battery charge model. To insure model fidelity, we fabricate a lightweight custom EV, perform extensive measurement, and derive model coefficients using multivariable regression analysis. We estimate the EV instantaneous power consumption of a given speed and route profiles and verify the estimation fidelity with a real test run data.

Selectively patterned masks: structured ASIC with asymptotically ASIC performance

Structured ASIC, which consists of a homogeneous array of tiles, suffers from large delay and area due to its inherent regularity. A new lithography method called selectively patterned masks (SPM) is proposed. It exploits special masks called masking masks and double exposure technique to allow more than one types of tiles to be patterned on the same wafer. The result is a heterogeneous array of tiles, which relaxes regularity in structured ASIC. A new structured ASIC based on SPM is proposed; tile and routing architectures, design flow, and tile packing and routing algorithm are all addressed. Experiments in 45-nm technology show that, compared to ASIC, the proposed structured ASIC exhibits 2.0 times of area when circuits are optimized for area and 1.2 times of delay when they are optimized for delay. Both figures represent substantial improvement over conventional structured ASIC.

Minimum-energy driving speed profiles for low-speed electric vehicles

Electric vehicles (EV) are rapidly invading the previous internal combustion engine vehicle (ICEV) market introducing not only environmental friendliness and a higher efficiency but a better ride quality, comfortness and performance. However, there still remain factors that the EV cannot reach the territory of ICEV such as a limited fully charged driving range per vehicle cost due to a low energy density of batteries compared with petroleum fuel. The ICEV has an up to 5 × longer driving range than that of EV as shown in Fig. 1. Common production EV shows only a quarter fully charged range of ICEV with a similar curb weight and a 50% higher price range. The fully charged range is much more crucial when it comes to EV. Running out of battery charge while driving results in serious inconvenience comparable to vehicle breakdown because of an orders of magnitude longer fuel charging time and lack of charging facilities.

Partially solar powered full electric vehicles

Electric Vehicles (EV) are known to have three times more energy efficient than petroleum internal combustion engine (ICE) vehicles. This is true if we do not consider electricity generation, transmission and vehicle battery charging efficiency. ICE vehicles have various vendor-specific technologies regarding fuel efficiency including engines, transmissions and their matching. EV, on the other hand, fuel efficiency is largely dependent on the vehicle weight thanks to simplified drivetrain such as direct drive without a transmission. Nevertheless, true energy efficiency of EV should be justified by the source of electricity. This paper introduces a custom, light-weight EV prototype for partial solar powered EV. We demonstrate the custom energy-efficient EV prototype and possibility of partially solar-powered EV.

ACCURATE GATE DELAY EXTRACTION FOR TIMING ANALYSIS OF BODY-BIASED CIRCUITS

Static body biasing is a circuit technique in which bias voltage is selected from more than one available voltage after manufacturing. It allows circuits to be designed at more favorable process corners; but effective application requires gate delays to be available for the new process corners, without the expense of re-characterizing individual gates. We show that the new delay of a gate (when body bias is applied) can be extrapolated from its old delay without body bias together with old and new delays of a few reference gates. Output transition time, which is another component of gate timing model, is extrapolated in a similar manner. Experiments with an industrial 32-nm gate library show that the average error in the new gate delays is less than 4.3%.

Reconfigurable thermoelectric generators for vehicle radiators energy harvesting

Conventional internal combustion engine vehicles (ICEV) generally have less than a 30% of fuel efficiency, and the most wasted energy is dissipated in the form of heat energy. The heat energy maintains the engine temperature for efficient combustion as a good aspect, but the amount of heat generation is excessive and eventually breaks the engine components unless advanced cooling system technologies are supported such as high-capacity radiators, elaborated water jackets, high-flow rate coolant pumps, etc. The excessive heat dissipation plays a key role on a poor fuel economy, but reclamation of the heat energy has not been a main focus of vehicle design. This work is first to propose a cross-layer, system-level solution to enhance thermoelectric generator (TEG) array efficiency introducing online reconfiguration of TEG modules. The proposed method is useful to any sort of TEG array to reclaim wasted heat energy because cooling and exhaust systems generally have different inlet and outlet temperatures. In this paper, we deploy the proposed method to vehicle radiator heat energy harvesting, which does not affect the vehicle performance while exhaust heat energy harvesting may disturb the combustion and emission control integrity. We introduce a novel TEG reconfiguration and maximize the TEG array output in spite of dynamic change of the coolant flow rate and temperature, which results in a huge variation in the coolant temperature distribution of inside the radiator. The proposed method enables all the TEG modules to run at or close to their maximum power points (MPP) under dynamically changing vehicle operating conditions. Experimental results show up to a 34% enhancement compared with a fixed array structure, which is a common practice.

Compressed On-Chip Framebuffer Cache for Low-Power Display Systems

A framebuffer memory is data storage for the displayed image, which is one of the major power consumers in display systems. This paper proposes a power reduction technique for the on-chip framebuffer cache (FBC) performing a compressed image data management. The proposed architecture stores the compressed image data in the on-chip FBC, and the display controller decompresses the image data on the fly and sends it to the liquid crystal display panel. The compression and decompression processes incur additional power consumption but achieve lower system-wide power consumption. We implement the proposed architecture in a field-programmable gate array platform to confirm power saving by actual measurement. Experiments demonstrate that the proposed on-chip FBC significantly reduces the number of the off-chip framebuffer memory accesses and saves a large portion of the system-wide power consumption accordingly.

Efficiency-driven design time optimization of a hybrid energy storage system with networked charge transfer interconnect

This paper targets at the state-of-art hybrid energy storage systems (HESSs) with a networked charge transfer interconnect and solves a node placement problem in the HESS, where a node refers to a storage bank, a power source, or a load device, with its distributed power converter. In particular, the node placement problem is formulated as how to place the nodes in a HESS such that the optimal total charge transfer efficiency is achieved, with accurate modelings of all kinds of different components in the HESS. The methodology of FPGA placement problem is adopted to solve the node placement in HESS by properly defining a cost function that strongly relates the charge transfer efficiency to the node placement, properties of HESS components, as well as applications of the HESS. An algorithm that combines a quadratic programming method to generate an initial placement and a simulated annealing method to converge to the optimal placement result is presented in this paper. Experimental results demonstrate the efficacy of the placement algorithm and improvements in the charge transfer efficiency for various problem setups and scales.

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning

A structured ASIC, one kind of programmable logic device (PLD), consists of a homogeneous array of programmable logic elements, or called tiles. The architecture of each tile is supposed to be very general so that any kind of logic can be implemented on it; this is the main reason why a structured ASIC has an inherently limited performance, together with a large area requirement compared to an ASIC. This balances the little mask cost of structured ASIC. We tilt this balance by introducing a small number of different types of tile, each with its own architecture, which can be deployed across different designs by the use of a simple blocking mask. This is made possible by a new photolithography concept called selectively patterned masks (SPM), which we propose. We address the practical issues of SPM, including mask cost and manufacturing time. We introduce the heterogeneous array of programmable logic (HAPL), which is a new structured ASIC which takes advantage of SPM. HAPL has its own tile and routing architectures, and supporting CAD tools for packing and routing. Extensive experiments in 45-nm technology are used to assess HAPL and compare it with ASIC. A HAPL design that is optimized for area is about twice the size of its ASIC counterpart. A delay-optimized HAPL design exhibits a post-layout delay which is, on average, 1.35 that of an equivalent ASIC.

Pulsed-V dd : Synchronous Circuit Design without Clock Network

Almost all digital circuits designed these days are synchronous ones. A clock is responsible for synchronization and is distributed via clock (distribution) network, which requires significant design time and effort and incurs extra area and wirelength. We advocate that synchronous circuit can be designed without clock network. Instead, power supply Vdd network is made to carry periodic negative pulses. A new sequencing element is proposed, which internally generates a positive pulse with each negative pulse on Vdd and then latches input data using that pulse. Since pulses are delivered over the Vdd network, which inherently has small RC value, skew becomes smaller, which is another advantage.