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Dive into the research topics where Severine Cheramy is active.

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Featured researches published by Severine Cheramy.


international solid-state circuits conference | 2016

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links

Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigne; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro-Panades; Cristiano Santos; Fabien Clermidy; Severine Cheramy; Frédéric Pétrot; Eric Flamand; Jean Michailos

By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4x4x2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2014

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

Papa Momar Souare; Vincent Fiori; A. Farcy; François de Crécy; Haykel Ben Jamaa; Andras Borbely; Perceval Coudrain; Jean-Philippe Colonna; Sebastien Gallois-Garreignot; Bastien Giraud; Severine Cheramy; C. Tavernier; Jean Michailos

This paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded in situ sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded in situ sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness.


IEEE Design & Test of Computers | 2016

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits

Perceval Coudrain; Papa Momar Souare; R. Prieto; Vincent Fiori; A. Farcy; Laurent Le Pailleur; Jean-Philippe Colonna; Cristiano Santos; Pascal Vivet; Haykel Ben-Jamaa; Denis Dutoit; François de Crécy; Sylvain Dumas; Christian Chancel; Didier Lattard; Severine Cheramy

This article describes heat dissipation challenges in 3-D ICs; using two case studies, it also presents insights and design guidelines for 3-D thermal management.


ieee international d systems integration conference | 2016

ITAC: A complete 3D integration test platform

Didier Lattard; L. Arnaud; Arnaud Garnier; Nicolas Bresson; Franck Bana; Roselyne Segaud; Amadine Jouve; Hélène Jacquinot; Stéphane Moreau; Karim Azizi-Mourier; C. Chantre; Pascal Vivet; Gaël Pillonnet; Fabrice Casset; F. Ponthenier; A. Farcy; Sandrine Lhostis; Jean Michailos; Alexandre Arriordaz; Severine Cheramy

System integration takes benefit from 3D stacking technology in a wide range of applications such as smart imagers, photonic, wide I/O memories and high-performance computing. The 700 mm2 ITAC 3D integration test platform contains a set of “Integrated Technological and Application Circuits” for process development, electrical and RF characterization, reliability, die stacking, warpage and underfilling studies, DC-DC converter and IntAct chip which is the full application chip. After a brief presentation of the targeted high performance computing application. The contributions integrated in the test platform are described with a particular focus on the 10 μm diameter 20 μm pitch die-to-die interconnects which is the key technology of the 3D stack. These test vehicles have been embedded on the same silicon to secure the application chip at all the steps from technology development to assembly and test.


Archive | 2015

Silicon Technologies for Nanoscale Device Packaging

Aurélie Thuaire; Gaëlle Le Gac; Guillaume Audoit; François Aussenac; Caroline Rauer; Emmanuel Rolland; Jean-Michel Hartmann; Anne-Marie Charvet; Hubert Moriceau; Pierrette Rivallin; Patrick Reynaud; Severine Cheramy; Nicolas Sillon; Xavier Baillin

We present our recent developments on silicon technologies dedicated to the packaging of nano-objects/nano-devices. These technologies aim at both protecting and electrically connecting a nanoscale device positioned on a perfect Si(001)-(2 × 1):H surface smoothed thanks to a 950 °C thermal treatment. The nano-device is connected to nanopads implanted on the silicon surface. Each nanopad is linked to a nanovia which is locally achieved by etching and filling processes operated in a FIB (Focused Ion Beam) equipment. Impacts of the FIB process on via morphology and properties are depicted. Nanopads are fabricated through the local implantation of arsenic, and the effect of the surface smoothing thermal treatment on the dopants diffusion length is estimated by simulation and then experimentally explored. Key process steps such as the etching of a deep cavity and the surface protection with a temporary cap are also described, and a first assembly consisting in a substrate equipped with nanopads and directly bonded with a cap substrate is presented.


symposium on vlsi technology | 2016

Fine charge sensing using a silicon nanowire for biodetection

Corentin Carmignani; Olivier Rozeau; Pascal Scheiblin; Aurélie Thuaire; Patrick Reynaud; Sylvain Barraud; T. Ernst; Severine Cheramy; M. Vinet

This paper proposes an extensive analysis of the impact of both structural effect and charge parameters on silicon nanowire-based biological sensors, for single-charge detection. These parameters are calibrated on physical and electrical characterizations and are subsequently introduced in a compact model to predict the signal over noise ratio (SNR). We finally propose rules for the design of nanowires and recommendations for the placement of the biological element, inducing the single charge release.


Archive | 2017

Nanopackaging of Si(100)H Wafer for Atomic-Scale Investigations

Delphine Sordes; Aurélie Thuaire; Patrick Reynaud; Caroline Rauer; Jean-Michel Hartmann; Hubert Moriceau; Emmanuel Rolland; Marek Kolmer; Marek Szymonski; Corentin Durand; Christian Joachim; Severine Cheramy; Xavier Baillin

Ultra-high vacuum (UHV) investigations have demonstrated a successful development of atomic nanostructures. The scanning tunneling microscope (STM) provides surface study at the atomic scale. However, the surface preparation is a crucial experimental step and requires a complex protocol conducted in situ in a UHV chamber. Surface contamination, atomic roughness, and defect density must be controlled in order to ensure the reliability of advanced UHV experiments. Consequently, a packaging for nanoscale devices has been developed in a microelectronic clean room environment enabling the particle density and contaminant concentration control. This nanopackaging solution is proposed in order to obtain a Si(001)-(2×1):H reconstructed surface. This surface is protected by a temporary silicon cap. The nanopackaging process consists in a direct bonding of two passivated silicon surfaces and is followed by a wafer dicing step into 1-cm2 dies. Samples can be stored, shipped, and in situ opened without any additional treatment. A specific procedure has been developed in order to open the nanopackaged samples in a UHV debonder, mounted in the load-lock chamber of a low-temperature STM system (LT-STM). Statistical large scan LT-UHV-SEM images and LT-UHV-STM images have been obtained enabling the surface study at the atomic resolution.


ieee international d systems integration conference | 2016

Heat spreading packaging solutions for hybrid bonded 3D-ICs

R. Prieto; Perceval Coudrain; Jean-Philippe Colonna; Y. Hallez; Christian Chancel; V. Rat; Sylvain Dumas; G. Romano; R. Franiatte; C. Brunet-Manquiat; Severine Cheramy; A. Farcy

Direct hybrid bonding is considered as one of the most promising technologies for high performance 3D-ICs. Its face-to-face structure allows significant inter-connexion capabilities. Nonetheless, it also implies increased thermal densities that will be reflected in both die tiers due to the lack of insulating barriers. This work investigates the thermal interactions between two hybrid bonded dice for different case scenarios. A specific test vehicle comprising heaters and temperature sensors have been designed. Packaging variables such as silicon thickness, substrate thermal design or TIM conductivity and thickness are studied.


ieee international d systems integration conference | 2016

Towards high density 3D interconnections

Severine Cheramy; Amandine Jouve; L. Arnaud; C. Fenouillet-Beranger; Perrine Batude; M. Vinet

After many years of packaging evolution as main industrial driver for 3D integration, even denser integration scheme have gained recently more interest. Slowdown of Moores law while maintaining the need of high performance and/or low power from one hand, and a combination of performance / form factor from the other, lead research to innovation and alternative solutions.


IEEE Transactions on Components, Packaging and Manufacturing Technology | 2016

Innovative Solutions for the Nanoscale Packaging of Silicon-Based and Biological Nanowires: Development of a Generic Characterization and Integration Platform

Aurélie Thuaire; Patrick Reynaud; Christophe Brun; Delphine Sordes; Corentin Carmignani; Emmanuel Rolland; Xavier Baillin; Severine Cheramy; Gilles Poupon

With their attractive intrinsic properties, such as morphology, autoassembling properties, and tailorability, nano-objects could provide alternative and innovative routes to current microelectronics and nanoelectronics. Further insight on their electrical properties, especially in terms of statistics and reproducibility, as well as on their potential integration into silicon-based electronics is, however, often required to be able to fully exploit their potential. This paper proposes an innovative approach using a generic structure allowing the study of nano-objects electrical properties. Regarding the nano-objects integration, a homogeneous approach is presented with the in situ fabrication of atomic wires as a possible planar interconnection system. A heterogeneous approach is described as well with the characterization and preliminary integration of biological material, such as deoxyribonucleic acid-based nanowires or amyloid fibers.

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Pascal Vivet

Centre national de la recherche scientifique

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Arianna Filoramo

Centre national de la recherche scientifique

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Didier Gasparutto

Centre national de la recherche scientifique

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Cristiano Santos

Universidade Federal do Rio Grande do Sul

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