Shadi M. Harb

Analytical Study of the Expected Number of Hops in Wireless Ad Hoc Network

Due to the randomness and mobility of ad hoc networks, estimating the average number of hops becomes very essential in multi-hop ad hoc networks, which is used as a key metric for performance comparison between multi-hop routing protocols; however, most current research derives the average number of hops based on simulations and empirical results, lacking the theoretical analysis of this essential metric. This paper presents a theoretical study of the expected number of hops between any two random nodes using typical modeling assumptions -an N-node randomly Poisson distributed connected network (i.e. for any two random nodes, they are connected by at least one path). The proposed theoretical analysis studies the relationship between the average number of hop counts and other critical ad hoc network parameters such as transmission range (r 0 ), node density (ρ), and area (A). At last, simulation results will be given to verify the theoretical analysis.

A VLSI High-Performance Priority Encoder Using Standard CMOS Library

A novel high-performance priority encoder design using standard CMOS library cell is proposed. The new encoder design implementation accommodates both high- and low-priority functionalities with scalable design structure through a special prefixing scheme. The prefixing scheme is applied to minimize the entire propagation delay and exploit the shared hardware between the high- and low-priority evaluation logics circuitry. The proposed encoder shows significant improvement in terms of speed, robustness for top-level floor plan routing, and modularity with pattern structure in compared to the existing encoder designs. Simulation results are conducted for different encoder inputs through 0.15-mum TSMC CMOS technology, where 32-bit priority encoder is used as a test vehicle for comparison improvement measurements. The expected results show that the 32-bit encoder is operating at a maximum of 667-MHz operating frequency with total count of 1106 transistors and a maximum power consumption of total 13.8 mW

High speed I/O and thermal effect characterization of 3D stacked ICs

This work focuses on characterizing the performance of the 3D TSVs under high speed transient simulation, which could potentially evaluate and verify the electrical models for these vertical connections. A Gunning Transceiver Logic (GTL) I/O on-chip test IC and a CML/Thermal test IC has been designed and sent for fabrication using the 3D FDSOI CMOS technology. The GTL I/O circuits are used to inject different data patterns at different frequencies across different tiers. A control MUX with Tri-state buffers and control logic can be used to switch between different I/O GTL drivers at different tiers. The GTL I/O test IC is dedicated to measure the NEXT/FEXT crosstalk between vertical connections by firing high speed signals from different tiers. The data-dependent-Jitter (DDJ) will be characterized by observing the eye diagram for a random and different data patterns. CML I/O circuits were designed to characterize high speed differential transmission, especially, the performance of high current buffers in the three tiered-system implementation. Differential signals were used to test the performance of through—silicon vias (TSV) and interconnect as the signals transmit from IC tier-to-tier. In addition, temperature sensors were integrated in order to model the 3D thermal performance as affected by the I/O drivers.

High speed digital CMOS divide-by-N fequency divider

A high-speed scalable programmable divide-by-N frequency divider is presented. The divider includes a new proposed state look-ahead parallel counter with a basic conventional D-type Flip-Flop (DFF) circuit. The counter is structured from two modules of 2-bit counter stages separated by DFF buffers, where all are triggered at the edge of the input clock. The reload circuit is a single DFF buffer, while the detecting count circuit is constructed from a two level decoder. The M-bit divider critical path delay, which is independent of technology, is approximated to [3.5 + Log4 (M)] of a unit delay close to a 2-input NAND gate. This results in a measured frequency, which slightly drops to about 6% against the increase of the divider bit size. Furthermore, the divider circuit is attractive for continued technology scaling since the architecture is based on using identical modules of small count of CMOS transistors with only threshold voltage technology limitations. The measure rate of the number of transistors is approximated to a linear increase of about 17% per a two-bit increase of the divider size. The presented 8-bit programmable divide-by-N frequency divider is capable of operating up to 2 GHz for a 1.35 V power supply voltage with a maximum power consumption of 16.78 mW and a maximum frequency divider factor of N=256 using the TSMC 0.15 mum digital CMOS process, and gives a measured area of 95*143 mum2 with a total count of 508 transistors.

Low-power content addressable memory with read/write and matched mask ports

A low-power content addressable memory (CAM) with read/write and mask match ports is proposed. The CAM cell is based on the conventional 6T cross-coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The readout port exploits a pre-charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit × 128-bit is designed using 0.18-µm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 µm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage.

A low-power CAM using a 12-transistor design cell

A low-power CAM design using a 12-transistor cell is proposed. The CAM cell is based on the conventional 6T cross- coupled inverters used for storing data with an addition of two NMOS transistors for reading out. In addition, the CAM has another four transistors for mask comparison operation through classical pre-charge operation. The read-out port exploits a pre- charge reading mechanism in order to alleviate the drawback of power consumption generated from sensing amplifiers and all other related synchronization circuits which are structured in every column in the memory. Thus, the read and match features can have concurrent operations. An experimental CAM structure of storage size 64-bit x 128-bit is designed using 0.18- μm CMOS single poly and three layers of metals measuring a cell die area of 24.4375 μm2 and a total silicon area of 0.269192 mm2. The circuit works up to 200 MHz in simulation with total power consumption of 0.016 W at 1.8-V supply voltage

Impact of Crosstalk on Signal Integrity of TSVs in 3D Integrated Circuits

A R T I C L E I N F O A B S T R A C T Article history: Received: 02 November, 2017 Accepted: 24 December, 2017 Online: 30 January, 2018 Through-Silicon-Vias (TSVs) are utilized for high density 3D integration, which induce crosstalk problems and impact signal integrity. This paper focuses on TSV crosstalk characterization in 3D integrated circuits, where several TSV physical and environmental configurations are investigated. In particular, this work shows a detailed study on the influence of signal-ground TSV locations, distances and their structural configurations on crosstalk. Embedded 3D testing circuits are also presented to evaluate the coupling effects between adjacent TSVs such as crosstalk induced delay and glitches for different crosstalk modes. Additionally, A 3D parallel Ring Oscillators testing structure is proposed to provide crosstalk strength coupling indicator between adjacent TSVs. Simulation results are conducted using a 3D electromagnetic field solver (HFSS) from Ansoft Corporation and a Spice-like simulator (ADS) from Keysight Technologies Corporation based on MIT 0.15μm 3DFDSOI process technology.

On-Chip Testing Schemes of Through-Silicon-Vias (TSVs) in 3D Stacked ICs

A R T I C L E I N F O A B S T R A C T Article history: Received: 02 June, 2017 Accepted: 09 July, 2017 Online: 23 July, 2017 This paper presents on-chip testing structures to characterize and detect faulty Through Silicon Vias (TSVs) in 3D ICs technology. 3D Gunning Transceiver Logic (GTL) I/O testing is proposed to characterize the performance of 3D TSVs in high speed applications. The GTL testing circuit will fire different data patterns at different frequencies to characterize the transient performance of TSVs. In addition, Different testing schemes based on an oscillation ring testing methodology are proposed to detect TSVs faults such as stuck-at, open, slope and delay degradation, and severe crosstalk TSVs coupling. A parallel ringbased oscillator test structure is proposed and simulated based on a high performance fully tunable electrical circuit pi-model where a single and coupled TSVs with ground-signalground (GSG) and ground-signal-signal-ground (GSSG) 3D vias configurations are used as a test vehicle for 3D interconnect characterization and test. Simulation results are presented using the Keysight/Agilent Advance Design System (ADS) and a standard 0.25 μm CMOS process.