William R. Eisenstadt

Combined differential and common-mode scattering parameters: theory and simulation

A theory for combined differential and common-mode normalized power waves is developed in terms of even and odd mode impedances and propagation constants for a microwave coupled line system. These are related to even and odd-mode terminal currents and voltages. Generalized s-parameters of a two-port are developed for waves propagating in several coupled modes. The two-port s-parameters form a 4-by-4 matrix containing differential-mode, common-mode, and cross-mode s-parameters. A special case of the theory allows the use of uncoupled transmission lines to measure the coupled-mode waves. Simulations verify the concept of these mixed-mode s-parameters, and demonstrate conversion from mode to mode for asymmetric microwave structures. >

S-parameter-based IC interconnect transmission line characterization

A methodology for extracting high-frequency IC interconnect transmission parameters directly from S-parameter measurements has been demonstrated using on-chip test structures. The methodology consists of: (1) building on-chip interconnect structures for microwave test, (2) characterizing and subtracting measurement system parasitics, (3) extracting the transmission line impedance and propagation constant (attenuation constant and phase constant) from the calibrated data, and (4) extracting the Telegraphers Equation transmission parameters (R, L, C, and G). Additional on-chip calibration permits subtraction of pad parasitic effects. This methodology is demonstrated over a 45-MHz to 20-GHz frequency range using an example 1-cm-long, 4- mu m-wide IC interconnect built in an advanced BiCMOS technology. Variations in interconnect impedance and capacitance indicate two signal propagation modes. Significant substrate-based loss is measured at microwave frequencies. >

High-speed VLSI interconnect modeling based on S-parameter measurements

A first-level-metal single-conductor IC interconnect model is developed for high-speed and high-density VLSI circuit design. The model shows interconnect circuit parameters that vary with frequency. Existing interconnect models exclude effects such as capacitive fringing and the influence of substrate conductance. The new model represents fine-line as well as wide-line interconnect behavior over a 20-GHz frequency range and includes these effects. The model parameters are compared to scattering parameter measurements as well as numerical simulations based on PISCES-II. Excellent agreement is shown with S-parameter measurements. >

LINC power amplifier combiner method efficiency optimization

Linear amplification using nonlinear components (LINC) is a method of vector summing two constant amplitude phase-modulated signals to achieve power amplification. The theoretical efficiency of the LINC power amplifier has been reported as 100% since highly efficient nonlinear constant amplitude amplifiers can be used. However, the 100% efficiency performance is only possible at one or two loads along the power output curve. The bulk of the papers regarding LINC has focused on clever implementations of the signal vector decomposition as well as methods to achieve highly linear signal separation. There has been little regard in the literature to the signal combiner implementation necessary to achieve the high power-added efficiency (PAE) of the LINC radio frequency (RF) power amplifier. Efficiency is not an intrinsic property of the combiner implementations, however, the combiner method is the single biggest contributor to efficient performance of a LINC RF power amplifier. This paper develops an analysis method that determines the efficiency of the LINC power amplifier as a function of the amplitude modulation statistics. This can be employed to design the RF communication system amplitude modulation characteristics and to tradeoff and optimize the RF transmitter PAE.

Pure-mode network analyzer for on-wafer measurements of mixed-mode S-parameters of differential circuits

A practical measurement system is introduced for measurement of combined differential and common-mode (mixed-mode) scattering parameters, and its operation is discussed. A pure-mode system measures network parameters of a differential circuit in the fundamental modes of operation, and has improved accuracy over a traditional network analyzer for the measurement of such circuits. The system is suitable for on-wafer measurements of differential circuits. The transformation between standard S-parameters and mixed-mode S-parameters is developed. Example microwave differential structures are measured with the pure-mode vector-network analyzer (PMVNA), and the corrected data is presented. These structures are simulated, and the simulated mixed-mode S-parameters correlate well with the measured data.

Embedded loopback test for RF ICs

This paper explores the use of on-chip or on-wafer loopback implementations for verifying performance of 5-GHz wireless local area network (WLAN) IC circuits. The loopback test diagram, the test-circuit design, and the characterization data are reported for subcircuits (attenuators, and switches) necessary to implement 5-GHz transceiver loopback. A loopback circuit that can be applied to transceiver loopback measurements is demonstrated. This research is exploratory in nature and is a first attempt at a new on-chip RF test technique.

A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-/spl mu/m CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design.

Bipolar Microwave RMS Power Detectors

A peak/RMS power detector with ges40 dB dynamic range is presented. The simulated frequency response is flat to 60GHz and the measured response is flat to 20 GHz. Analysis shows that the Meyer detector, originally developed as a peak detector, can be used for RMS detection with an error less than 0.5dB over an approximately 20 dB range, comparable to the popular RF/microwave diode detector. The range for RMS detection is extended by cascading several stages of attenuators and detectors, leading to a circuit suitable for applications such as embedded RFIC test. The power detector is only 700times550 mum2 including all AC and DC bond pads

Accuracy estimation of mixed-mode scattering parameter measurements

The pure-mode vector network analyzer (PMVNA) provides direct measurement of differential circuits. Residual error models are derived for the PMVNA and a traditional four-port vector network analyzer (FPVNA). The residual error models are used to calculate the maximum and root-mean-square uncertainties in measurements of mixed-mode scattering parameters of a typical differential amplifier. The uncertainties produced by the PMVNA are compared to the transformed mixed-mode S-parameters of the FPVNA. The PMVNA is shown to have lower uncertainty when measuring differential devices.

On-chip self-calibration of RF circuits using specification-driven built-in self test (S-BIST)

In the nanometer design regime, analog and RF circuits are expected to be increasingly susceptible to process, noise and thermal variations. Shifting threshold voltages on the NMOS and PMOS devices of a mixer, LNA or power amplifier, for example, can affect the design specifications of such circuits (such as gain). Thermal variations can affect carrier mobilities of NMOS and PMOS devices differently, further affecting circuit performance. To solve these problems, a new self-calibration approach driven by a Specification-driven built-in self test procedure (S-BIST) is proposed. This S-BIST procedure uses alternate specification test techniques to predict the performance specifications of the circuit-under-test from the S-BIST response. The results of the S-BIST procedure are used to change the operating point of the circuit to maximally compensate the analog/RF circuit for loss of performance. The proposed S-BIST approach has been applied to a 2.4-GHz low noise amplifier and performs well in the presence of temperature and process variations.