Shahriar Rokhsaz

A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system

A full CMOS seventh-order linear phase filter based on g/sub m/-C biquads with a -3-dB frequency of 200 MHz is realized in 0.35-/spl mu/m CMOS process. The linear operational transconductance amplifier is based on complementary differential pairs in order to achieve both low-distortion figures and high-frequency operation. The common-mode feedback (CMFB) employed takes advantage of the filter architecture; incorporating the load capacitors into the CMFB loop improves further its phase margin. A very simple automatic tuning system corrects the filter deviations due to process parameter tolerances and temperature variations. The group delay ripple is less than 5% for frequencies up to 300 MHz, while the power consumption is 60 mW. The third-harmonic distortion is less than -44 dB for input signals up to 500 mV/sub pp/. The filter active area is only 900 /spl times/ 200 /spl mu/m/sup 2/. The supply voltages used are /spl plusmn/1.5 V.

A 2-V/sub pp/ 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning

A CMOS 80-200-MHz fourth-order continuous-time 0.05/spl deg/ equiripple linear phase filter with an automatic frequency tuning system is presented. An operational transconductance amplifier based on transistors operating in triode region is used and a circuit that combines common-mode feedback, common-mode feedforward, and adaptive bias is introduced. The chip was fabricated in a 0.35-/spl mu/m process; filter experimental results have shown a total harmonic distortion less than -44 dB for a 2-V/sub pp/ differential input with a single 2.3-V power supply. The group delay ripple is less than 4% for frequencies up to 1.5 f/sub c/. The frequency tuning error is below 5%.

A Full On-Chip CMOS Clock-and-Data Recovery IC for OC-192 Applications

In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-mum CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10-12 when the input pseudorandom bit sequence (PRBS) data pattern has a pattern length of 215 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (Ulpp) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 Ulpp by applying PRBS data with a pattern length of 231 - 1.

A 1.8V CMOS, 80-200MHz continuous-time 4th order 0.05/spl deg/ equiripple linear phase filter with automatic tuning system

A 1.8V CMOS 80-200MHz continuous time 4th-order 0.05/spl deg/ equiripple linear phase filter with an automatic tuning system is presented. An operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a wide linear input range (1.8V/sub ppd/ peak-to-peak differential input with a single 1.8V power supply) and a wide transconductance tuning range. A novel and high performance system which integrates common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptative-bias into one circuit is introduced. The filter is based on Gm-C biquads and the post-layout simulation results in a 0.18/spl mu/m process have shown a THD of less than -40dB with a 1.8V/sub ppd/ input and a 80-200MHz cutoff frequency tunable range. The group delay ripple is less than 3% for frequencies up to 1.4 times of the cutoff frequency and over the whole frequency tuning range. A simple automatic tuning system which adjusts the transconductance of the OTA is used to compensate the process parameter variations.

Power supply induced jitter modeling of an on-chip LC oscillator

This paper concentrates on developing a closed-form small signal model to determine the power supply induced jitter (PSIJ) for on chip LC based voltage controlled oscillator (VCO). To determine the source of the PSIJ, we have developed a Mathcad model which is used to optimize the VCO design in order to achieve the lowest possible jitter allowed by its architecture.