Shaiful Nizam Mohyar

Single inductor dual output DC-DC converter design with exclusive control

This paper proposes a single inductor dual output (SIDO) DC-DC Converter with exclusive control circuit. We propose two kinds of converter: a buck-buck and a boost-boost converter. Multiple voltage outputs are controlled exclusively, using error voltage feedback. This approach requires few additional components (a switch, a diode and a comparator), requires no current sensors and does not depend on the value of output voltage or output current. We describe circuit topologies, operation principles and simulation results.

Time-to-digital converter architecture with residue arithmetic and its FPGA implementation

This paper describes a time-to-digital converter (TDC) architecuture with residue arithmetic or Chinese Remainder theorem. It can reduce the hardware and power significantly compared to a flash type TDC while keeping comparable performance. Its FPGA implementation and measurement resuts show the effectiveness of our proposed architecture.

DAC linearity improvement algorithm with unit cell sorting based on magic square

This paper proposes a switching algorithm using magic square properties to improve the linearity of a unary DAC by canceling random and systematic mismatch effects among unit current (or capacitor) cells. Simulation results and discussions are provided for DAC linearity comparison in case that the proposed magic square and conventional algorithms are used.

Low noise figure 2.4 GHz down conversion CMOS mixer for wireless sensor network application

This work proposed a low noise figure 2.4 GHz down-conversion CMOS mixer for wireless sensor network (WSN) application using 0.13-μm Silterra technology. The proposed down-conversion mixer converts a high radio frequency (RF) signal from 2.4 GHz to an intermediate frequency (IF) of 100 MHz through the use of a local oscillator signal (LO) of 2.3 GHz. The proposed mixer employs a double balance Gilbert-cell topology with integrated input matching at the input stage and a low pass filter at the IF stage. The simulation results indicate that the proposed mixer obtains lower noise figure (NF) of 5.21 dB with an input third-order intercept point (IIP3) of 0 dB. Furthermore, the conversion gain (CG) of 8.6 dB is achieved with the power consumption of 1.57 mW at 1.8 V supply voltage.

I-Q signal generation techniques for communication IC testing and ATE systems

This paper describes application of a complex band-pass (BP) ΔΣ DA modulator to I-Q signal generation for I-Q balance testing of communication IC as well as ATE system usage. First we explain that the complex BP ΔΣ DA modulator is superior to two real-BP ΔΣ DA modulators regarding to noise-shaping characteristics. Then we examine the characteristics of the complex BP ΔΣ DA modulator and its extension - a complex multi-BP modulator - as well as its newly derived Data Weighted Averaging (DWA) algorithm for its linearity enhancement. We also propose a digital self-calibration technique, and show their simulation results. Their combination is also investigated. We discuss application of our proposed techniques to IC testing.

SFDR Improvement Algorithms for Current-Steering DACs

This paper presents algorithms for improving spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) — targeted at communication applications — by minimizing both current-source mismatches and glitches. Conventional segmented current-steering DACs suffer from static mismatches among current sources which cause nonlinearity and degrade SFDR, though glitch energy is relatively small. The data-weighted averaging (DWA) algorithm can reduce static current source mismatch effects, but it increases the effects of glitch energy. Here we investigate the use of both conventional Switching-Sequence Post-Adjustment (SSPA) calibration and One–Element-Shifting (OES) methods in order to reduce the effects of both nonlinearity and glitch energy. For further improvement, we propose and investigate a fully-digital combined algorithm to reduce static current source mismatch effects with minimal increase in the glitch energy. We also did simulations of the effect of combining these two compensation methods. Our MATLAB simulations show that the combined algorithm can improve SFDR performance by 24 dB, 22dB and 2dB compared to conventional thermometer-coded, one-element-shifting and SSPA methods respectively in some conditions. When we take current mismatch into account, the combined algorithm causes glitch energy to increase by only 0.02 to 0.2 % compared to the other three methods alone.

Digital calibration algorithm for half-unary current-steering DAC for linearity improvement

This paper introduces an algorithm called 3-stage current sorting (3S-CS) in half-unary weighted current cells to improve the linearity of a current-steering digital-to-analog converter (DAC). Based our statistical analysis and simulation results, the proposed algorithm improves the DAC static linearity as well as its dynamic performance.

Linearity enhancement algorithms for I-Q signal generation — DWA and self-calibration techniques

This paper describes two linearity enhancement algorithms for I-Q signal generation using a multi-bit complex band-pass (BP) ΔΣ DA modulator targeted for communication IC design and testing applications. The first one is a complex multi-band-pass data-weighted-averaging algorithm and the second is a self-calibration algorithm. The generated I, Q signals can be up-converted to a high frequency signal. We present their principles and MATLAB simulation results.

Single-Inductor Dual-Output DC-DC Converter Design with Exclusive Control

This paper proposes a single inductor dual output (SIDO) DC-DC converter with an exclusive control circuit. We propose two kinds of converter: a buck-buck and a boost-boost converter. Multiple voltage outputs are controlled exclusively, using error voltage feedback. This approach requires a few additional components (a switch, a diode and a comparator), but requires no current sensors and does not depend on the value of output voltage or output current. We describe circuit topologies, operation principles and simulation results.