Sohiful Anuar Zainol Murad

An Excellent Gain Flatness 3.0–7.0 GHz CMOS PA for UWB Applications

This letter presents an excellent gain flatness CMOS power amplifier (PA) for UWB applications at 3.0-7.0 GHz in TSMC 0.18 μm CMOS technology. The UWB PA proposed here employs a current-reused technique to enhance the gain at the upper end of the desired band, a shunt and a series peaking inductors with a resistive feedback at the second stage to obtain the wider and flat gain, while shunt-shunt feedback helps to enhance the bandwidth and improve the output wideband matching. The measurement results indicated that the input return loss (S11) less than -6 dB, output return loss (S22) less than -7 dB, and excellent gain flatness approximately 14.5 ±0.5 dB over the frequency range of interest. The output 1 dB compression of 7 dBm, the output third-order intercept point (OIP3) of 18 dBm, and a phase linearity property (group delay) of ±178.5 ps across the whole band were obtained with a power consumption of 24 mW.

Low Group Delay 3.1–10.6 GHz CMOS Power Amplifier for UWB Applications

This letter proposes the design of a low group delay ultra-wideband (UWB) power amplifier (PA) in CMOS technology. The PA design employs a three-stage cascade common source topology that has a different design concept from other multi-stage topology to provide a broad bandwidth characteristic, gain flatness of , and low group delay variation of . A resistive shunt feedback technique is adopted at the first stage of the amplifier to achieve good input matching, which controls the upper frequency of the UWB system. The third stage realizes the gain at the lower corner frequency and the second stage is used to smooth the flatness of the gain curve. By using this method, the proposed design has the lowest group delay variation among the recently reported CMOS PAs for 3.1 to 10.6 GHz applications.

High efficiency, good linearity, and excellent phase linearity of 3.1-4.8 GHz CMOS UWB PA with a current-reused technique

This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-μm CMOS technology. The UWB PA proposed here employs cascode topology with a current-reused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement results indicated that the input return loss (S11) was less than -5 dB, output return loss (S22) was less than -8 dB, and average power gain of 10.3 dB with a flatness about 0.8 dB. The input 1 dB compression point about -2 dBm and excellent phase linearity (group delay) of ±135 ps across the whole band were obtained. Moreover, a very high power added efficiency (PAE) of 40.5% at 4 GHz with 50 Ω load impedance was achieved with a power consumption of 24-mW.

A 3.0–7.5 GHz CMOS UWB PA for group 1~3 MB-OFDM application using current-reused and shunt-shunt feedback

The design of a 3.0–7.5 GHz UWB CMOS power amplifier (PA) for group 1~3 MB-OFDM UWB applications in TSMC 0.18-µm CMOS technology is presented. The UWB PA proposed in this paper uses a current-reused technique to enhance the gain at the upper end of the desired band, and the resistive feedback at the second stage is used to obtain gain flatness. The shunt-shunt feedback is used to enhance bandwidth and improve output wideband matching. In addition, the cascode topology with an additional common-source stage was used to achieve high power gain. The post-layout simulation results indicated that the input return loss (S11) was less than −5 dB, output return loss (S22) was less than −7 dBm, and average gain was approximately 10 dB over the frequencies ranges of interest. The output 1-dB compression point above 0 dBm, the output third-order intercept point (OIP3) was 10 dBm, and average PAE of 12%. Moreover, an excellent phase linearity property (group delay) of ±137.7 ps across the whole band was obtained with a power consumption of 15 mW.

A 2.4 GHz 0.18-µm CMOS Class E single-ended power amplifier without spiral inductors

This paper describes the design of a 2.4-GHz CMOS Class E single-ended power amplifier (PA) for wireless applications in TSMC 0.18-µm CMOS technology. The Class E PA proposed in this paper realizes all inductors with bondwires for the higher quality factor to increase PA performance and to reduce chip size. The single-ended topology is employed because most existing components designed to be driven by PAs are single-ended. The cascode topology with a self-biasing technique is used to prevent device stress and to decrease the requirement for additional bond pads. The measurement results indicate that the PA delivers 19.2 dBm output power and 27.8% power added efficiency with 3.3-V power supply into a 50 Ω load. The chip area is 0.37 mm2.

A review of LNA topologies for wireless applications

This paper presents the reviews of few previous works for low noise amplifier design (LNA). This paper will explore several recent architectures of LNA but focused on four techniques of topologies which are forward body bias, self-biased inverter, common source cascade and cascode technique. Those architectures are able to minimize power consumed in a typical CMOS for wireless sensor network (WSN). Besides, high gain, low noise, input and output matching are also reviewed. As to provide extremely low power and also optimized all characteristics aspects, the performance for each topologies then are discussed. Further research will be conducted based on these four topologies comparisons in order to design a new successful LNA.

A 3.0–5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications

This paper presents a high linearity and low power up-conversion mixer at 3.0–5.0 GHz for UWB applications in TSMC 0.18-µm CMOS technology. The design based on Gilbert-cell active double-balanced mixer using a capacitor located in parallel with the intrinsic gate-source capacitor of a transconductance stage for high linearity. The source degeneration inductors helps to improve linearity and IF input matching. The current injection is employed to increase gain and obtained low power. The up-conversion mixer converts an input of 100 MHz intermediate frequency (IF) signal to an output of 3.0–5.0 GHz radio frequency (RF) signal. The post-layout simulation results indicated that the proposed mixer achieves a higher input third order intercept point (IIP3) of 13.5-dBm, convention gain of 2.3-dB and low power of 7.1-mW at 1.2-V power supply.

A 3.1 - 4.8 GHz CMOS UWB Power Amplifier Using Current Reused Technique

This paper describes the design of a 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using TSMC 0.18-µm CMOS technology. The UWB PA proposed in this paper employs cascode topology with an additional common source stage to achieve high power gain. The current reused technique is implemented to enhance the gain at the upper end of the desired band for gain flatness and the resistive feedback at the second stage is used to improve wideband matching. The post-layout simulation results indicate that the gain at the upper end of desired frequency is increased about 11 dB and the gain flatness of 18.4±1 dB is achieved, improved the linearity at an input 1-dB compression point of - 10.6 dBm, and consumes low power (22 mW) at 1.0 V DC supply voltages.

A 6–10.6 GHz CMOS PA with common-gate as an input stage for UWB transmitters

The design of a 6.0–10.6 GHz UWB CMOS power amplifier (PA) for ultra-wideband (UWB) transmitters in TSMC 0.18-µm CMOS technology is presented. The UWB PA proposed in this paper employing a common gate (CG) amplifier as the input stage for wideband matching and the current-reused technique is used to save the power consumption and to enhance gain at the higher frequency. The shunt peaking inductors were used to improve gain flatness and to increase the total bandwidth of the circuit. The post-layout simulation results show that the input return loss (S11) was less than −8 dB, output return loss (S22) was less than −10 dBm, and average gain was approximately 11 dB over the frequencies ranges of interest. The input and output 1-dB compression point is −12 dBm and 0 dBm, respectively. Moreover, an excellent phase linearity property (group delay) of ±55.8 ps across the whole band was obtained with power consumption of 18 mW. The chip area is 0.77 mm2.

High efficiency CMOS Class E power amplifier using 0.13 µm technology

This paper presents the design of a 2.4-GHz CMOS Class E power amplifier (PA) for wireless applications in Silterra 0.13-μm CMOS technology. The Class E PA proposed in this paper is a single-stage PA in a cascode topology in order to minimize the device stress problem. All transistors are arranged in parallel to decrease on-resistance for high efficiency with on-chip input and output impedance matching. The simulation results indicate that the PA delivers 11.9 dBm output power and 53% power added efficiency (PAE) with 1.3-V power supply into a 50-Ω load. The chip layout is 0.27 mm2.