Yajun Ha
National University of Singapore
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Publication
Featured researches published by Yajun Ha.
The Journal of Supercomputing | 2002
Yajun Ha; Serge Vernalde; Partrick Schaumont; Marc Engels; Rudy Lauwereins; Hugo De Man
A virtual framework that uses both hardware and software reconfigurable objects is presented. The new framework supports both networked hardware and software reconfiguration. In such a virtual framework, the networked reconfiguration users only need to develop a single service description targeted on a single hardware and software platform. The service is able to write once, and run everywhere. That facilitates the new service deployment and maintenance. We present the components, design flow and implementation aspects of the virtual framework.
field programmable logic and applications | 2002
Yajun Ha; Radovan Hipik; Serge Vernalde; Diederik Verkest; Marc Engels; Rudy Lauwereins; Hugo De Man
Like real general-purpose processors, Java Virtual Machines (JVMs) need hardware acceleration for computationally intensive applications. JVMs however require that platform independence can be maintained while resorting to hardware acceleration. To this end, we invented a scheme to seamlessly add hardware support to Suns HotSpot JVM. By means of run-time profiling, we select the most heavily used Java methods for execution in Field Programmable Gate Arrays (FPGA) hardware. Methods running in hardware are designed at compiletime, but the bitstreams are generated at run-time to guarantee platform independence. If no method improves the performance by running in hardware, all Java methods still can run in software with trivial run-time overheads. We have implemented this hardware supported JVM. The results show that hardware acceleration for JVMs can be achieved while maintaining platform independence for domain specific applications.
field programmable logic and applications | 2001
Yajun Ha; Bingfeng Mei; Patrick Schaumont; Serge Vernalde; Rudy Lauwereins; Hugo De Man
The rapid development of the Internet opens wide opportunities for various types of network services. Development of new network services need the support of a powerful design framework. This paper describes such a design framework that can help service providers to build platform independent hardware-software co-designed services. Those new services consist of both software and hardware components, which can be reconfigured through the network. The new design framework can be considered as a Java framework with a hardware extension. Part of the measurement results and an application demonstrator are given.
asia and south pacific design automation conference | 2001
Yajun Ha; Geert Vanmeerbeeck; Patrick Schaumont; Serge Vernalde; Marc Engels; Rudy Lauwereins; Hugo De Man
A virtual interface between Java and FPGA for networked reconfiguration is presented. Through the Java/FPGA interface, Java applications can exploit hardware accelerators with FPGAs for both functional flexibility and performance acceleration. At the same time, the interface is platform independent. It enables the networked application developers to design their applications with only one interface in mind when considering the interfacing issues. The virtual interface is part of our work to build a platform-independent deployment framework for the networked services. In the framework, both the software and hardware components of services can be platform independently described and deployed.
IEEE Transactions on Biomedical Circuits and Systems | 2010
Haiting Tian; Shakith Fernando; Hock Wei Soon; Zhang Qiang; Chunxi Zhang; Yajun Ha; Nanguang Chen
Pseudorandom single photon counting is a novel time-resolved optical measurement method, which is advantageous over convention techniques in terms of data-acquisition speed and system cost. As a critical component of the pseudorandom single photon counter, the photon arriving time digitizer should be storage efficient for a high photon counting rate, while maintaining good time accuracy. We report an ultra storage-efficient time digitizer for a pseudorandom single photon counter in this paper, which is based on the asynchronous serial communication and can store the arriving time of every photon in 1-b memory space. In addition, a novel comb-wave modulator is proposed to achieve the dc balance required for asynchronous serial communication. Our prototype implemented on field-programmable gate arrays provides a time resolution of 400 ps. It can register up to 4.2-Giga photon arriving time tags with 1024 × 32-b memory space.
field-programmable custom computing machines | 2001
Yajun Ha; Patrick Schaumont; Serge Vernalde; Marc Engels; Rudy Lauwereins; H. De Man
A SW/HW interface API for Java/FPGA co-designed applets is presented in this paper. The co-designed applets consists of Java software part and FPGA hardware part. With the developed virtual SW/HW interface API, software part of the applets can transparently utilize FPGAs to implement some of their computationally intensive algoritjms in a networked environment. A demonstrator of web MPEG-1 player had been constructed for this API.
international symposium on circuits and systems | 2013
Yi Wang; Yajun Ha
Power analysis attack is an efficient way to retrieve the sensitive information from the hardware implementation of modern cryptographic algorithms, such as Advance Encryption Standard (AES). First-order masking could defend against Differential Power Analysis (DPA) attack without extra hardware support. However, it is vulnerable to Higher-Order Differential Power Analysis (HODPA) attack. HODPA attack could be avoided using a higher order masking scheme, but it takes up huge hardware resources. In this paper, we propose a low cost shuffling scheme for FPGA based AES implementations, which is able to efficiently resist against HODPA attack. We reuse our previous masked S-box proposed in [20-21] to reduce hardware resources and defend against glitch attacks. Also, we reorder the executing sequence of the MixColumns and the AddRoundKey transformations in the first-second, the last and the second to last rounds. It is difficult for the attackers to find the “real” attacking points in our proposed design. The experimental results show that our proposed design is only 5.6% larger than the masking only scheme.
field-programmable logic and applications | 2008
Fujie Wong; Yajun Ha
With the increasing process variations in advanced semiconductor technologies, fault tolerance has become one of several essential issues in building Field Programmable Gate Arrays (FPGAs). Unfortunately, there has been much less fault tolerance work previously done on FPGA interconnects, which take up to 90% of an FPGA device, than on its logic blocks. In view of this, we develop a low overhead connection block architecture, which improves the fault tolerance of FPGA interconnects. By testing 10 MCNC benchmarks on the new architecture, FPGA fault tolerance reaches levels comparable to adding 2 extra wire tracks per channel, with the average timing overhead below 2.5% and the area overheads of only 2.5% - 4%.
international conference on electronics circuits and systems | 1999
Yajun Ha; M. F. Li; Ai Qun Liu
A class-AB low voltage high driving capability CMOS buffer amplifier using improved quasi-complementary output stage and error amplifiers with adaptive loads is developed. Improved quasi-complementary output stage makes it more suitable for low voltage applications, while adaptive load in error amplifier is used to increase the driving capability and reduce the sensitivity of the quiescent current to process variation. The circuit has been fabricated in 0.8 /spl mu/m CMOS process. With 300 /spl Omega/ load in a /spl plusmn/1.5 V supply, its output swing is 2.42 V. The mean value of quiescent current for eight samples is 204 /spl mu/A, with the worst deviation of 17%.
field-programmable logic and applications | 2008
Shakith Fernando; Xiaolei Chen; Yajun Ha
The poor scalability of current mesh-based FPGA interconnection networks is impeding our attempts to build next-generation FPGA of larger logic capacity. A few alternative interconnection network architectures have been proposed for future FPGAs, but they still have several design challenges that need to be addressed. In this paper, we propose sFPGA, a scalable FPGA architecture, which is a hybrid between hierarchical interconnection and network-on-chip. The logic resources in sFPGA are organized into an array of logic tiles. The tiles are connected by a hierarchical network of switches, which route data packets over the network. In addition, we have proposed a design flow for sFPGA which integrates current design flows seamlessly. By doing a case study in our emulation prototype, we have validated our sFPGA design flow.