Shakti Shankar Rath
Texas Instruments
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Featured researches published by Shakti Shankar Rath.
IEEE Transactions on Circuits and Systems | 2012
Sunav Choudhary; Pritam Mukherjee; Mrityunjoy Chakraborty; Shakti Shankar Rath
The “sum of power of two (SPT)” is an effective format to represent filter coefficients in a digital filter which reduces the complexity of multiplications in the filtering process to just a few shift and add operations. The canonic SPT is a special sparse SPT representation that guarantees presence of at least one zero between every two non-zero SPT digits. In the case of adaptive filters, as the coefficients are updated with time continuously, conversion to such canonic SPT forms is, however, required at each time index, which is quite impractical and requires additional circuitry. Also, as the position of the non-zero SPT terms in each coefficient word changes with time, it is not possible to carry out multiplications involving the coefficients via a few fixed “shift and add” operations. This paper addresses these problems, in the context of a SPT based realization of adaptive filters belonging to the sign-LMS family. Firstly, it proposes a bit serial adder that takes as input two numbers in canonic SPT and produces an output also in canonic SPT, which is then extended to the case where one of the inputs is given in 2s complement form. This allows weight updating purely in the canonic SPT domain. It is also shown how the canonic SPT property of the input can be used to reduce the complexity of the proposed adder. For multiplication, the canonic SPT word for each coefficient is partitioned into non-overlapping digit pairs and the data word is multiplied by each pair separately. The fact that each pair can have at the most one non-zero digit is exploited further to reduce the complexity of the multiplication.
international conference on green circuits and systems | 2010
Shakti Shankar Rath; Mrityunjoy Chakraborty
The sign-LMS algorithm is a popular adaptive filter that requires only addition/subtraction but no multiplication in the weight update loop. To reduce the complexity of multiplication that arises in the filtering part of the sign-LMS algorithm, a special radix-4 format is presented in this paper to represent each filter coefficient. The chosen format guarantees sufficient sparsity which in turn reduces the multiplicative complexity as no partial product needs to be computed when the multiplicand is a binary zero. Care, is, however taken to ensure that the weight update process generates the updated weight also in the same chosen radix-4 format, which is ensured by developing an algorithm for adding a 2s complement number with a number given in the adopted radix-4 format.
Archive | 2006
Sami Issa; Baher Haroun; Shakti Shankar Rath
Archive | 2000
Suhas R. Kulhalli; Supriyo Palit; Sindhuja Sridharan; Shakti Shankar Rath; Anand Hariraj Udupa
Archive | 2003
Sami Issa; Baher Haroun; Shakti Shankar Rath
Archive | 2003
Nitin Agarwal; Shakti Shankar Rath
Archive | 2003
Sami Issa; Baher Haroun; Shakti Shankar Rath
Archive | 2003
Anand Hariraj Udupa; Visvesvaraya A. Pentakota; Shakti Shankar Rath; Gautam Salil Nandi; Vineet Mishra; Ravishankar S. Ayyagari; Nitin Agarwal
Archive | 2009
Sandeep Mallya Perdoor; Abhaya Kumar; Shakti Shankar Rath
Archive | 2016
Shakti Shankar Rath; Rishubh Khurana; Vineet Mishra