Shaloo Rakheja

Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects

Interconnects are considered as one of the grandest challenges that gigascale and terascale integrations face because of the delay they add to critical paths, the power they dissipate, the noise and jitter they induce on one another, and their vulnerability to electromigration. Recent studies on novel computational state variables such as electron spin have demonstrated that interconnects will continue to be an ever-growing challenge, even for post-complementary metal-oxide-semiconductor (CMOS) switches. The novel 2-D carbon-based material graphene has demonstrated remarkable electrical properties that make it a viable candidate to implement interconnects in both electrical and spintronic domains. In this paper, physical models of the electron transport parameters such as electron mean free path (MFP), diffusion coefficient, mobility, and resistance per unit length are presented for both bulk (2-D) and narrow (1-D) graphene nanoribbons (GNRs) as a function of the interconnect dimensions, edge roughness, and Fermi-energy shift. The potential of multilayer GNR (ML-GNR) as electrical interconnects is explored by taking into account the finite interlayer resistivity between the multiple layers within the ML-GNR stack. The spin-relaxation length in graphene is obtained using some theoretical estimates on the spin-orbit coupling (SOC) introduced due to ripples in graphene. It is found that, in pure graphene, the spin-relaxation length could be longer than 10 μm; however, the presence of adatoms limits the spin-relaxation length in graphene to only 1-2 μm at room temperature. The models developed in this paper are used to benchmark graphene interconnects against their conventional copper/low- κ interconnects in both electrical and spintronic domains. The results offer important insights about the advantages and limitations of graphene interconnects and provide guidelines for technology development for this emerging interconnect technology.

Performance and Energy-per-Bit Modeling of Multilayer Graphene Nanoribbon Conductors

In this paper, physical models are derived for the effective resistance of multilayer graphene nanoribbon (m-GNR) interconnects. The impact of finite resistive coupling between the layers for top contacted m-GNR interconnects is considered. It is found that the addition of more parallel layers does not necessarily translate into a decrease in the overall resistance of m-GNR interconnects. Rather, the improvement in the effective resistance saturates with an increase in the number of layers. The optimal number of layers to minimize the delay and the energy-delay product of m-GNR interconnects is also evaluated. It is found that the optimal number of layers is a function of the interconnect length, interlayer resistance, and the kind of contact that is used. It is demonstrated that, for short interconnect lengths, m-GNR interconnects with smooth edges perform better compared to copper wires.

An Ambipolar Virtual-Source-Based Charge-Current Compact Model for Nanoscale Graphene Transistors

A compact physics-based ambipolar-virtual-source (AVS) model is presented that describes carrier transport in both unipolar and ambipolar regimes in quasi-ballistic graphene field-effect transistors (GFETs). The transport model incorporates two separate virtual sources for electrons and holes and is supplemented by a self-consistent channel-charge-partitioning model valid from drift-diffusive to ballistic transport conditions. The model comprehends the asymmetry introduced by different contact resistances for electrons and holes. The AVS model has a limited number of parameters, most of which have a physical meaning and can easily be extracted from device characterization. The model has been extensively calibrated with experimental dc I-V and s-parameter measurements of devices with gate lengths from 650 to 40 nm. This has allowed the scaling of mobility and VS source injection velocity of carriers with gate length to be investigated for the first time. The new compact model yields continuous currents and charges and can easily be used in the design and analysis of circuits and systems implemented with GFETs.

Circuit Simulation of Magnetization Dynamics and Spin Transport

In this paper, compact circuit models for spintronic devices have been developed by manipulating the underlying physical equations. We have simulated, via circuit simulation: 1) the magnetization dynamics governed by the Landau-Lifshitz-Gilbert (LLG) equation and 2) the spin transport physics governed by the spin drift-diffusion equation. The models have been validated using numerical and analytical solutions of the LLG equation and the spin drift-diffusion equations, respectively. Simulations of an all-spin logic device demonstrate the applications of the developed models in device and circuit simulation.

Interconnects for Novel State Variables: Performance Modeling and Device and Circuit Implications

Fundamental laws of physics will severely limit the “scaling” of silicon FETs beyond the 2020 technology roadmap. There is a need to look for an alternate switching paradigm that can overcome the limitations of the current Si FET technology. Nanoelectronic switches that work with state variables other than electron charge are being investigated by researchers. Some of these post-CMOS technologies hold the promise to extend Moores law beyond the technology year 2020. Any new logic that aims at replacing the CMOS logic must be complemented with an interconnect technology that can transmit information encoded in the new computational variable between different physical locations of the chip. The focus of this paper is to map new logic technology with its respective interconnect technology. In this paper, comprehensive physical models of transport mechanisms that can be utilized for novel state variable transport through these novel interconnects are developed. An upper bound on speed of these interconnects is obtained, and a comparison is drawn between novel and CMOS interconnects. A comparison of delay of novel interconnects with CMOS interconnects provides important insights into the material, device, and circuit implications of these new interconnects.

Impact of Dimensional Scaling and Size Effects on Spin Transport in Copper and Aluminum Interconnects

In this paper, compact models of spin-relaxation lengths (SRLs) in copper and aluminum interconnects by incorporating contributions to spin relaxation from phonon-induced and defect-induced scatterings are developed. The proposed models have been exhaustively calibrated with experimental data from mesoscopic lateral spin valves. The compact models are used to predict the SRL in ultrascaled copper and aluminum interconnects with cross-sectional dimensions of only few hundreds of nm2. Even though the SRL in bulk copper can be as large as 400 nm, it is predicted that SRL can become sub-100 nm for a 7.5-nm-wide channel in the presence of nominal size effects. It is found that the SRL in aluminum is more than that in copper for the same size effects and interconnect cross-sectional dimensions. The degradation in SRL in aluminum with size effects is slower than that in copper. Using the compact models for SRL in conjunction with spin-diffusion theory, spin injection and transport efficiency (SITE) for metallic interconnects in a conventional spin-valve configuration is quantified in the presence of phonon and defect scatterings.

Modeling and optimization for multi-layer graphene nanoribbon conductors

Analytical models are developed for effective resistance of two dimensional resistor networks and applied to multi-layer graphene nanoribbon (GNR) interconnects. Improvement in effective resistance with additional GNR layers is estimated and optimal number of layers to minimize delay and Energy-delay-product (EDP) are quantitatively derived. Since longer interconnects have better coupling between layers, the optimal number of layers increases with length. Other potential applications of the model including graphene contact for solar cells are briefly discussed.

An Improved Virtual-Source-Based Transport Model for Quasi-Ballistic Transistors—Part I: Capturing Effects of Carrier Degeneracy, Drain-Bias Dependence of Gate Capacitance, and Nonlinear Channel-Access Resistance

In this paper, an improved physics-based virtual-source (VS) model to describe transport in quasi-ballistic transistors is discussed. The model is based on the Landauer scattering theory, and incorporates the effects of: 1) degeneracy on thermal velocity and mean free path of carriers in the channel; 2) drain-bias dependence of gate capacitance and VS charge, including the effects of band nonparabolicity; and 3) nonlinear resistance of the extrinsic device region on gm -degradation at high drain currents in the channel. The improved charge model captures the phenomenon of reduction in VS charge under nonequilibrium transport conditions in a quasi-ballistic transistor.

Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations

With continued shrinking of device dimensions on chip, major advancements in intra chip interconnect technology are required to minimize delay, energy dissipation and cross-talk. In this paper, two alternative on-chip interconnect technology options are studied, namely the plasmonic and optical interconnects. It is shown that plasmonic interconnects can be 3 orders of magnitude faster than minimum sized CMOS interconnects at the 2016 technology node. However, their propagation length is limited to few microns and hence they can be used only as short local interconnects. Energy per bit of plasmonic interconnects is shot-noise limited and it increases exponentially with interconnect length. Cross-over length beyond which plasmonic interconnects become less energy efficient compared to CMOS interconnects is calculated. It is found to be 10 μm for Ag cylindrical plasmonic waveguides of 100-nm diameter embedded in SiO2 dielectric at free-space wavelength of 1μm. Although plasmonic interconnects show potential as future local interconnects, plasmonic switches are needed for their implementation at the GSI(GigaScale Integration) level. Without plasmonic switches the energy and circuit overhead associated with signal conversion will be prohibitive. Optical interconnects, on the other hand, are limited to be used only at the global level due to the fundamental limitations on their size. Although the native interconnect delay of optical interconnects is quite less, their bandwidth density is limited due to the fundamental limitations on the minimum pitch. Wavelength division multiplexing is identified as one of the solutions towards increasing the bandwidth density of optical interconnects. Critical length beyond which optical interconnects offer higher bandwidth compared to copper interconnects is identified to be equal to the chip edge in absence of WDM. In presence of 4 channel WDM, the critical length improves to 0.4cm. Critical length assessment based on energy comparison with CMOS interconnect is evaluated to be 0.15cm.

Modeling Interconnects for Post-CMOS Devices and Comparison With Copper Interconnects

Power dissipation in charge-based technology is the biggest roadblock toward miniaturizing circuits. Quantum-mechanical tunneling and subthreshold leakage current will ultimately limit scaling of silicon field-effect transistors. To continue Moores law scaling, it is imperative that devices working with a state variable other than electron charge are sought for. Examples of alternate state variables include electron spins, pseudo-spins in graphene, direct and indirect excitons, plasmons, and phonons. At the same time, interconnection aspects of devices utilizing novel state variables must be considered early on. This paper provides a framework to quantify energy dissipation in interconnects for novel state variables. Models for energy per bit are then used along with previously derived models for delay of interconnects for novel state variables to compare performance and energy dissipation of novel interconnects with complementary metal-oxide-semiconductor (CMOS) interconnects. Comparison results provide important insights into material, device, and circuit implications of post-CMOS technologies.