Vachan Kumar

Evaluation of the Potential Performance of Graphene Nanoribbons as On-Chip Interconnects

Interconnects are considered as one of the grandest challenges that gigascale and terascale integrations face because of the delay they add to critical paths, the power they dissipate, the noise and jitter they induce on one another, and their vulnerability to electromigration. Recent studies on novel computational state variables such as electron spin have demonstrated that interconnects will continue to be an ever-growing challenge, even for post-complementary metal-oxide-semiconductor (CMOS) switches. The novel 2-D carbon-based material graphene has demonstrated remarkable electrical properties that make it a viable candidate to implement interconnects in both electrical and spintronic domains. In this paper, physical models of the electron transport parameters such as electron mean free path (MFP), diffusion coefficient, mobility, and resistance per unit length are presented for both bulk (2-D) and narrow (1-D) graphene nanoribbons (GNRs) as a function of the interconnect dimensions, edge roughness, and Fermi-energy shift. The potential of multilayer GNR (ML-GNR) as electrical interconnects is explored by taking into account the finite interlayer resistivity between the multiple layers within the ML-GNR stack. The spin-relaxation length in graphene is obtained using some theoretical estimates on the spin-orbit coupling (SOC) introduced due to ripples in graphene. It is found that, in pure graphene, the spin-relaxation length could be longer than 10 μm; however, the presence of adatoms limits the spin-relaxation length in graphene to only 1-2 μm at room temperature. The models developed in this paper are used to benchmark graphene interconnects against their conventional copper/low- κ interconnects in both electrical and spintronic domains. The results offer important insights about the advantages and limitations of graphene interconnects and provide guidelines for technology development for this emerging interconnect technology.

Performance and Energy-per-Bit Modeling of Multilayer Graphene Nanoribbon Conductors

In this paper, physical models are derived for the effective resistance of multilayer graphene nanoribbon (m-GNR) interconnects. The impact of finite resistive coupling between the layers for top contacted m-GNR interconnects is considered. It is found that the addition of more parallel layers does not necessarily translate into a decrease in the overall resistance of m-GNR interconnects. Rather, the improvement in the effective resistance saturates with an increase in the number of layers. The optimal number of layers to minimize the delay and the energy-delay product of m-GNR interconnects is also evaluated. It is found that the optimal number of layers is a function of the interconnect length, interlayer resistance, and the kind of contact that is used. It is demonstrated that, for short interconnect lengths, m-GNR interconnects with smooth edges perform better compared to copper wires.

Modeling and optimization for multi-layer graphene nanoribbon conductors

Analytical models are developed for effective resistance of two dimensional resistor networks and applied to multi-layer graphene nanoribbon (GNR) interconnects. Improvement in effective resistance with additional GNR layers is estimated and optimal number of layers to minimize delay and Energy-delay-product (EDP) are quantitatively derived. Since longer interconnects have better coupling between layers, the optimal number of layers increases with length. Other potential applications of the model including graphene contact for solar cells are briefly discussed.

Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for bumps, vias and connectors, and coupled multiconductor transmission lines for traces. The six-port transfer matrix approach enables easy computation of the transfer function, as well as near-end and far-end crosstalk. The intersymbol interference is accounted for by computing the pulse response for the worst case bit pattern. Furthermore, the models developed here are used to optimize the data-rate and trace width for each of the links, so that the aggregate bandwidth obtained per joule of energy supplied to the link is maximized. The modeling and optimization approach developed here serves as a good platform to compare the air-gap interconnects against BP, PCB, and SI interconnects on lossy dielectrics. It is shown that air-gap interconnects can provide an aggregate bandwidth improvement of 3x-4x for BP links at a comparable energy per bit, and a 5x-9x improvement in aggregate bandwidth of PCB links at the expense of 20% higher energy per bit. For SI links, airgap interconnects are shown to provide a 2x-3x improvement in aggregate bandwidth and a 1x-1.5x improvement in energy per bit.

Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations

With continued shrinking of device dimensions on chip, major advancements in intra chip interconnect technology are required to minimize delay, energy dissipation and cross-talk. In this paper, two alternative on-chip interconnect technology options are studied, namely the plasmonic and optical interconnects. It is shown that plasmonic interconnects can be 3 orders of magnitude faster than minimum sized CMOS interconnects at the 2016 technology node. However, their propagation length is limited to few microns and hence they can be used only as short local interconnects. Energy per bit of plasmonic interconnects is shot-noise limited and it increases exponentially with interconnect length. Cross-over length beyond which plasmonic interconnects become less energy efficient compared to CMOS interconnects is calculated. It is found to be 10 μm for Ag cylindrical plasmonic waveguides of 100-nm diameter embedded in SiO2 dielectric at free-space wavelength of 1μm. Although plasmonic interconnects show potential as future local interconnects, plasmonic switches are needed for their implementation at the GSI(GigaScale Integration) level. Without plasmonic switches the energy and circuit overhead associated with signal conversion will be prohibitive. Optical interconnects, on the other hand, are limited to be used only at the global level due to the fundamental limitations on their size. Although the native interconnect delay of optical interconnects is quite less, their bandwidth density is limited due to the fundamental limitations on the minimum pitch. Wavelength division multiplexing is identified as one of the solutions towards increasing the bandwidth density of optical interconnects. Critical length beyond which optical interconnects offer higher bandwidth compared to copper interconnects is identified to be equal to the chip edge in absence of WDM. In presence of 4 channel WDM, the critical length improves to 0.4cm. Critical length assessment based on energy comparison with CMOS interconnect is evaluated to be 0.15cm.

Design and fabrication of low-loss horizontal and vertical interconnect links using air-clad transmission lines and through silicon vias

In this paper we present the design and fabrication of air-clad planar transmission lines and TSVs that can be used as horizontal and vertical chip-chip interconnects. Performance improvement by using heterogeneous air-clad dielectric is presented for these two types of interconnect structures that establishes the basic motivation for fabricating these structures. The design data is verified by performing simulation using 3D full-wave solver HFSS. We outline the process flow for air-clad transmission lines and TSVs in detail. Several challenges in the fabrication of air-clad structures are also discussed.

BEOL Scaling Limits and Next Generation Technology Prospects

This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.

Analytical models for the frequency response of multi-layer graphene nanoribbon interconnects

Analytical models for frequency response of multilayer graphene interconnects are obtained by a general multi-conductor analysis approach. The dependence of frequency response on the number of layers is studied for two types of contacts: top and side contacts. Although virtually all experiments on multi-layer graphene use top contacts that couple only to the top layer, the analytical models available consider side contacts that couple to all the layers. It is shown that for side contacts, the frequency response improves continuously with number of layers, unlike the top contacts, which show very little improvement beyond a few layers. The delay and energy-delay-product obtained from the frequency response are minimized at some optimal number of layers, which is dependent on the interconnect length.

Modeling, optimization and benchmarking of chip-to-chip electrical interconnects with low loss air-clad dielectrics

Analytical models are developed for pulse response of chip-to-chip interconnects modeled as lossy transmission lines. The novel compact physical models capture the losses due to skin effect and dielectric losses and predict both the pulse height and width at the receiver. The work presented in this paper demonstrates the use of these models for optimization of data-rate and interconnect geometry in order to minimize energy-per-bit and maximize bandwidth-density simultaneously. Further, the model is applied to explore and quantify the potential benefits of low-k air-clad dielectrics that reduce dielectric losses. The model predicts a maximum improvement of ideal air dielectric over a lossy GETEK dielectric to be roughly 5–6 times in both energy-per bit and bandwidth-density. Additionally, the optimizations provided in the paper set the minimum requirements for optical interconnects in order to outperform electrical interconnects.

Impact of On-Chip Interconnect on the Performance of 3-D Integrated Circuits With Through-Silicon Vias: Part II

3-D integration using through-silicon vias (TSVs) can decrease interconnect length and improve chip performance. In this paper, electrical links consisting of TSVs and horizontal wires are designed, fabricated, and measured to analyze TSV capacitance and link delay. Compact models for the capacitance of a TSV surrounded by variable number of ground TSVs are developed and compared with measurements. The impact of TSV placement and scaling on link performance is further analyzed. The results demonstrate that placing TSVs closer to their drivers can effectively improve the performance of 3-D integrated circuit (3-D IC) links. Moreover, link delay is significantly improved by scaling TSV geometry to the point that 3-D IC links become on-chip wire limited.