Shang-Tse Chuang

Scaling internet routers using optics

Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to make efficient use of their expensive long-haul links. In this paper we consider how optics can be used to scale capacity and reduce power in a router. We start with the promising load-balanced switch architecture proposed by C-S. Chang. This approach eliminates the scheduler, is scalable, and guarantees 100% throughput for a broad class of traffic. But several problems need to be solved to make this architecture practical: (1) Packets can be mis-sequenced, (2) Pathological periodic traffic patterns can make throughput arbitrarily small, (3) The architecture requires a rapidly configuring switch fabric, and (4) It does not work when linecards are missing or have failed. In this paper we solve each problem in turn, and describe new architectures that include our solutions. We motivate our work by designing a 100Tb/s packet-switched router arranged as 640 linecards, each operating at 160Gb/s. We describe two different implementations based on technology available within the next three years.

Practical algorithms for performance guarantees in buffered crossbars

This paper is about high capacity switches and routers that give guaranteed throughput, rate and delay guarantees. Many routers are built using input queueing or combined input and output queueing (CIOQ), using crossbar switching fabrics. But such routers require impractically complex scheduling algorithms to provide the desired guarantees. We explore how a buffered crossbar-a crossbar switch with a packet buffer at each crosspoint-can provide guaranteed performance (throughput, rate, and delay), with less complex, practical scheduling algorithms. We describe scheduling algorithms that operate in parallel on each input and output port, and hence are scalable. With these algorithms, buffered crossbars with a speedup of two can provide 100% throughput, rate, and delay guarantees.

A 2 Gb/s/pin CMOS asymmetric serial link

The design of an asymmetric serial link poses a number of tradeoffs for the designer. This paper describes measurements from a 0.25 /spl mu/m CMOS test chip which show that a properly designed asymmetric link can achieve 2 Gb/s using single-ended signalling with a bit-error rate <10/sup -14/.

A load-balanced switch with an arbitrary number of linecards

The load-balanced switch architecture is a predicting way to scale router capacity. It requires no centralized scheduler, requires no memory operating faster than the line-rate which can be built using a fixed, optical mesh. In a recent paper it is explained how to prevent packet missequencing and provide 100% throughput for all traffic patterns, and described the design of 100 Tb/s router using technology available within three year there is one major problem with the load-balanced switching makes the basic mesh architecture impractical: Because the optical mesh must be uniform, the switch does not work when one or more linecards is missing or has failed. Instead we can use the passive optical switch architecture with MEMS switches the reconfigured only when linecards are added and deleted, all the router to function when any subset of linecards is presently working. In this paper we derive an expression for the number of MEMS switches that are needed, and describe an algorithm to configure them. We prove that the algorithm will be a always correct configuration in polynomial time, and show example of its running time

A 50 Gb/s 32/spl times/32 CMOS crossbar chip using asymmetric serial links

A 32/spl times/32 synchronous crossbar chip was designed in a 0.27 /spl mu/m CMOS technology for use in a high-speed network switch. The crossbar chip uses 32 Asymmetric Serial Links to achieve high speed at the interfaces and to reduce both power and area. The crossbar switch core is implemented with static CMOS multi-stage multiplexers with multicast capability. The chip operates successfully with links running at 1.6 Gb/s. The measured bit-error-rate is <10/sup -14/ when all channels and the switch core are operating. The crossbar chip consumes 5 W and provides a total bandwidth above 50 Gb/s.

Using hardware to configure a load-balanced switch

Efficient router architectures should have predictable throughput and scalable capacity, as well as internal optical technology (such as optical switches and wavelength division multiplexing) that can increase capacity by reducing power consumption. The load-balanced switch is a promising way to scale router capacity. In this 100-terabit-per-second router, an optical switch spreads traffic evenly among linecards. When the network operator adds or removes linecards, reconfiguring the switch can be time consuming, but a polynomial-time algorithm drastically reduces the required memory-intensive operations, yielding a switch-reconfiguration time below 50 ms.