Shannon Dunn

Line width roughness control for EUV patterning

Controlling line width roughness (LWR) is a critical issue in extreme ultraviolet lithography (EUVL). High sensitivity, high resolution, and low LWR are required for EUV lithography resist. However, simultaneously achieving optimal properties through chemical tuning alone is difficult. The track process is one of the factors that impacts LWR. Enhancing track processes in EUV lithography is thus critical to controlling LWR. This paper describes an approach to mitigating LWR based on optimizing track-based and etch-based processes. It also presents the results of our newly developed track-based smoothing process as well as the results of combining several track-based techniques. The latest LWR performance from using track-based techniques, optimized track processes, and etch-based techniques will be highlighted.

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

SADP for BEOL using chemical slimming with resist mandrel for beyond 22nm nodes

The fundamental limits of optical lithography have driven semiconductor processing research to push the envelope. Double patterning (DP) techniques including litho-etch litho-etch (LELE), litho-litho etch (LLE), and self-aligned double patterning (SADP) have become standard vernacular for near term semiconductor processing as EUV is not yet ready for high volume production. The challenge, even with techniques like LLE and SADP, remains that printing small lines on tight pitches (for LLE) or even small lines on relaxed pitches for mandrel/spacer combinations is not trivial. We have demonstrated a track-based slimming technique that can produce sub-25 nm resist lines for either SADP or LLE DP processes. Our work includes results for varying shrink amounts at different target critical dimensions (CD) and for multiple pitches. We also investigated CD uniformity (CDU) and defectivity. In particular, optimization of the amount of slimming is critical as it allows for much greater process latitude at the lithography step. In addition to the lithography work, we have continued the processing for both integration schemes to include oxide deposition and etch for SADP and through etch performance for DP. We have demonstrated sub 45 nm pitch structures. The wide variety of process uses, as well as the ability to achieve a large range of shrink amounts shows that track based slimming is a viable solution to achieve target CD and pitch values for sub 22 nm technology node.

Towards manufacturing of advanced logic devices by double-patterning

As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes, alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting 16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity (CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure (CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction method. The effects of the exposure field size are also compared between a small field and the full field. Included in all the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

Assessment of negative tone development challenges

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

450mm etch process development and process chamber evaluation using 193i DSA guided pattern

In the Global 450mm Equipment Development Consortium (G450C), a 193i guided directed self-assembly (DSA) pattern has been used to create structures at the 14nm node and below. The first guided DSA patterned wafer was ready for etch process development within a month of the G450C’s first 193i patterned wafer availability with one litho pass. Etch processes were scaled up from 300mm to 450mm for a 28nm pitch STI stack and a 40nm pitch M1 BEOL stack. The effects of various process parameters were investigated to fine tune each process. Overall process window has been checked and compared. Excellent process stability results were shown for current etch chambers.

450mm lithography status for high volume manufacturing

The Global 450mm Consortium (G450C), which is located at the SUNY Poly campus in Albany, NY was created to develop and evaluate a manufacturing tool set for 450mm wafers. The Lithography cell at G450C consists of a Nikon NSR-S650D 193nm immersion scanner and a SCREEN SOKUDO DUO DT-4000 track. The Lithography cell was installed and qualified in 2015, and with over a year of tool availability we have been able to perform extensive testing on the system to determine the equipment readiness for volume manufacturing. For the purposes of this paper we are focusing on the Edge Placement Error (EPE) [1] contributors of Critical Dimension Uniformity (CDU) and Overlay [2]. We will show the initial results as well as the improvements that have been made since tool acceptance. The 450mm results will be compared to 300mm tools in production today, as well as against the seven nanometer node (N7) expected requirements. Lastly, we plan to demonstrate the Nikon scanner’s ability for focus control on stressed or bowed wafers, which are characteristic challenges of large silicon substrates. This paper will showcase the current 450mm lithography performance for CDU on both Line/Space (LS) and Contact Hole (CH) patterns. We will demonstrate the process window for LS and CH features on multiple resists specially formulated for 450mm. Both Post Exposure Bake (PEB) tuning on the SCREEN track as well as CDU Master (CDUM) Corrections from the Nikon Turnkey Solution software suite will be utilized for performance improvements on 450mm wafers. The G450C goal is to drive CDU down to less than 1nm 3σ across the entire wafer with 1.5mm edge exclusion zone.” In addition to our test masks, G450C has designed a three layer mask set and with these masks we gathered “on product” CDU performance on a Back End Of Line (BEOL) metal stack. In the current reality of high volume manufacturing, multi-patterning is used to achieve the required Critical Dimension (CD) and pitch combination. The largest contributor to EPE is scanner overlay performance. We will demonstrate the Single Machine Overlay (SMO) performance as well as some Mix and Match Overlay (MMO) results. The lithography cell at G450C is the only 450mm linked lithography cell in the world. In order to create MMO wafers we were required to expose the first print at the Nikon factory in Japan and etch them at G450C to generate an align-to layer. As the wafers’ size scales, so do some of the process effects including film stress and wafer bow. The current G450C BEOL integrated process has measured wafer bow of up to 350um. We will demonstrate how the S650D measures the wafer topography and adjusts the exposure to compensate for wafer bow.

Immersion lithography scanner resolution performance demonstration on 450mm substrates

The Global 450mm Consortium (G450C) has completed its 5th year of developing and evaluating manufacturing 450mm tool sets. This paper focuses on how the lithography cell resolution performance has progressed from tool acceptance to current day. Initial data will be shown as well as the iterative and final data following process and equipment improvements that have been implemented over the course of the G450C program. This paper will demonstrate both line/space and contact hole Critical Dimension Uniformity (CDU), one of the key indicators of resolution performance, as well as process window performance on multiple masks and resist processes. The CDU performance shows significant improvement after three main factors were implemented: custom-made photoresist, track process optimization, and Nikon Turnkey CDU Master software application. It will be demonstrated that with the implementation of optimized photoresist, Post Exposure bake (PEB) tuning and CDU Master correction that CDU results of <1nm 3σ may be achieved on 450mm wafers. The final CDU results for contact hole and line/space will be compared to 300mm production tools as well as the N7 and N10 expected requirements. Besides a traditional 6% Attenuated Phase Shifting Mask (APSM), G450C litho also utilizes thin Opaque MoSi On Glass Mask (OMOG). Process window comparisons will be evaluated on both mask technologies for all of the resist processes. In addition to the test masks, G450C completed the design of a three layer mask set with resist based Optical Proximity Correction (OPC) modeling and gathered “on product” CDU performance on a Back End Of Line (BEOL) metal stack.

450mm Cu single damascene BEOL process with 20nm half-pitched features

At 450mm wafer area, the first Cu BEOL module process was demonstrated with a single damascene structure using low-k ILD, TiN metal hard mask and guided 20nm half-pitched lamella BCP DSA patterning. It showed the potential opportunities, technical feasibility and further challenges for coming needs for 450mm equipment.

STI 28nm pitch guided DSA to enable the 450mm tools qualification and transition

One of the options to reduce the cost related to the next generation of devices in the semiconductor industry is the scale up of the wafer size from 300mm to 450mm. The 450mm transition requires the development and qualification of new tools and processes. G450C, a partnership between five international integrated circuit (IC) makers and CNSE (College of Nanoscale Science and Engineering), has been created to lead this transition. Patterned wafers are necessary to test and demonstrate these 450mm tools. The challenge has been to develop and validate a patterning process — capable of producing advanced-node-relevant features — in a timely manner to enable the process and tool demonstrations. Based on the provided and available 450mm processes and tools, a 28nm pitch STI (Shallow Trench Isolation) structure on a 450mm wafer was developed. This feature was made possible using a 193nm immersion lithography DSA (Directed Self Assembly) technique. This paper will update G450C program status and show process results obtained on 450mm wafers using an STI structure.