Lior Huli

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

Line width roughness control for EUV patterning

Controlling line width roughness (LWR) is a critical issue in extreme ultraviolet lithography (EUVL). High sensitivity, high resolution, and low LWR are required for EUV lithography resist. However, simultaneously achieving optimal properties through chemical tuning alone is difficult. The track process is one of the factors that impacts LWR. Enhancing track processes in EUV lithography is thus critical to controlling LWR. This paper describes an approach to mitigating LWR based on optimizing track-based and etch-based processes. It also presents the results of our newly developed track-based smoothing process as well as the results of combining several track-based techniques. The latest LWR performance from using track-based techniques, optimized track processes, and etch-based techniques will be highlighted.

Resist process applications to improve EUV patterning

Roughness control is a key technical issue in extreme ultraviolet (EUV) lithography. It applies to both line and space (L/S) and contact hole (C/H) structures. Recently, SEMATECH and Tokyo Electron Limited (TEL) developed several track-based techniques, including developer optimization, FIRM™ (Finishing up by Improved Rinse Material), and smoothing to reduce structural roughness. The combination of these techniques improved line width roughness (LWR) about 25% from the 2011 baseline of 32 nm L/S. C/H structures were also tested with the combination process. This paper describes our latest L/S and C/H roughness performance post-lithography and postetch. A feasibility study of negative tone develop (NTD) resists for EUV is also included.

SADP for BEOL using chemical slimming with resist mandrel for beyond 22nm nodes

The fundamental limits of optical lithography have driven semiconductor processing research to push the envelope. Double patterning (DP) techniques including litho-etch litho-etch (LELE), litho-litho etch (LLE), and self-aligned double patterning (SADP) have become standard vernacular for near term semiconductor processing as EUV is not yet ready for high volume production. The challenge, even with techniques like LLE and SADP, remains that printing small lines on tight pitches (for LLE) or even small lines on relaxed pitches for mandrel/spacer combinations is not trivial. We have demonstrated a track-based slimming technique that can produce sub-25 nm resist lines for either SADP or LLE DP processes. Our work includes results for varying shrink amounts at different target critical dimensions (CD) and for multiple pitches. We also investigated CD uniformity (CDU) and defectivity. In particular, optimization of the amount of slimming is critical as it allows for much greater process latitude at the lithography step. In addition to the lithography work, we have continued the processing for both integration schemes to include oxide deposition and etch for SADP and through etch performance for DP. We have demonstrated sub 45 nm pitch structures. The wide variety of process uses, as well as the ability to achieve a large range of shrink amounts shows that track based slimming is a viable solution to achieve target CD and pitch values for sub 22 nm technology node.

Double patterning combined with shrink technique to extend ArF lithography for contact holes to 22nm node and beyond

Lithography becomes much more challenging when CD shrinks to 22nm nodes. Since EUV is not ready, double patterning combined with Resolution Enhancement Technology (RET) such as shrink techniques seems to be the most possible solution. Companies such as TSMC[1] and IBM[2] etc. are pushing out EUV to extend immersion ArF lithography to 32nm/22nm nodes. Last year, we presented our development work on 32nm node contact (50nm hole at 100nm pitch) using dry ArF lithography by double patterning with SAFIER shrink process[3]. To continue the work, we further extend our dry litho capability towards the 22nm node. We demonstrated double patterning capability of 40nm holes at 80nm pitch using ASML XT1400E scanner. It seems difficult to print pitches below 140nm on dry scanner in single exposure which is transferred into 70nm pitch with double patterning. To push the resolution to 22nm node and beyond, we developed ArF immersion process on ASML XT1700i-P system at the College of Nanoscale Science and Engineering (Albany, NY) combined with a SAFIER process. We achieved single exposure process capability of 25nm holes at 128nm pitch after shrink. It enables us to print ~25nm holes at pitch of 64nm with double patterning. Two types of hard mask (HM), i.e. TIN and a-Si were used in both dry and immersion ArF DP processes. The double patterning process consists of two HM litho-shrink-etch steps. The dense feature is designed into two complementary parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 21/2 depending on design. The complete pattern is formed after the two HM litho-shrink-etch steps are finished.

Assessment of negative tone development challenges

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

SEMATECH's cycles of learning test for EUV photoresist and its applications for process improvement

With current progress in exposure source power, novel resist materials, and post processing techniques, EUV is getting closer to the production environment. As reported continuously, SEMATECH established cycles of learning program. The data generated from the program has been utilized to measure current state of the art of EUV photoresist for production or pilot line use. Thanks to SEMATECH core and associate members’ attention to the project, numerous EUV samples have been tested and they were based on the best performing EUV resists from associate members. This year we completed the evaluations for under-layers, lines and spaces, and contact holes. We also applied track based techniques to drive both low line edge roughness control and enlarge the process window with techniques such as FIRMTM and track based smoothing process. In this paper we will discuss about the results from cycles of learning test and show post-processing results of the three best line and space resists when combined with different FIRMTM materials.

Defect detection strategies and process partitioning for SE EUV patterning (Conference Presentation)

The key challenge for enablement of a 2nd node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma (291x) and e-beam systems, find it difficult to detect the main yield-detracting defects post-develop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield. This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors .

Driving down defect density in composite EUV patterning film stacks

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TELTM) are continuously collaborating to develop manufacturing quality processes for EUVL. In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.

Evaluation of novel processing approaches to improve extreme ultraviolet (EUV) photoresist pattern quality

Recently there has been a great deal of effort focused on increasing EUV scanner source power; which is correlated to increased wafer throughput of production systems. Another way of increasing throughput would be to increase the photospeed of the photoresist used. However increasing the photospeed without improving the overall lithographic performance, such as local critical dimension uniformity (L-CDU) and process window, does not deliver the overall improvements required for a high volume manufacturing (HVM). This paper continues a discussion started in prior publications [Ref 3,4,6], which focused on using readily available process tooling (currently in use for 193 nm double patterning applications) and the existing EUV photoresists to increase photospeed (lower dose requirement) for line and space applications. Techniques to improve L-CDU for contact hole applications will also be described.