Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Shanshan Du.
international conference on solid-state and integrated circuits technology | 2008
Yi Huang; Shanshan Du; Haiyang Zhang; Haihua Chen; Qiuhua Han; Shih-Mou Chang
This paper presents an overview of 65 nm poly gate fabrication challenges emerged during the device performance & yield enhancement on 300 mm wafer. The proposed solutions hinge on the improvement of some critical process parameters in 65 nm gate etch such as, critical dimension uniformity (CDU), through-pitch etch bias (TPEB), line width roughness (LWR) and poly gate profile. More than 7% yield enhancement and improved Vmin (the minimum voltage at which the addressed device function correctly) distribution have been obtained with improved CDU&TPEB.
Archive | 2010
Shanshan Du; Qiuhua Han; Yi Huang; Linlin Zhao
Archive | 2010
Yi Huang; Shanshan Du; Haiyang Zhang
Archive | 2009
Yi Huang; Shanshan Du; Haiyang Zhang
Archive | 2008
Yi Huang; Shanshan Du; Haihua Chen; Haiyang Zhang
Archive | 2010
Shanshan Du; Qiuhua Han; Yi Huang; Linlin Zhao
Archive | 2011
Shanshan Du; Qiuhua Han; Haiyang Zhang
Archive | 2010
Shanshan Du; Qiuhua Han; Yi Huang
Archive | 2008
Haihua Chen; Haiyang Zhang; Shanshan Du
Archive | 2008
Haiyang Zhang; Shanshan Du; Haihua Chen; Qingtian Ma
Collaboration
Dive into the Shanshan Du's collaboration.
