Shanshan Yong

Design and implementation of a MAC protocol for a wearable monitoring system on human body

Wearable sensor devices organized in a Wireless Body Area Network (WBAN) have been widely used in healthcare monitoring. However, energy efficiency and reliability are still major problems in this area. An efficient media access control (MAC) protocol is a promising solution. Traditional protocols are too generic and usually used in busy frequency band which are not suitable for a particular medical scenario. On the basis of Human Body Communication (HBC), a MAC protocol for WBAN is proposed in this work which can avoid interference and make non-RF technique available. It also helps reduce power consumption and prolong the network lifetime by reducing transmitting frequency and increasing sleep time of a WBAN node. The protocol utilizes a new ALOHA medium access which defines user priorities for different types of data. Compared with the Slotted ALOHA (S-Aloha) suggested in the IEEE 802.15.6 standard, our method shows good performance in terms of power consumption when the information rate is low. In addition, a circuit system is designed for a medical scenario according to our new protocol.

A multi-bit encoder and FM0/Miller decoder design for UHF RFID reader digital baseband

The encoder and decoder are the keys of security and error-rate for UHF RFID reader. In this paper, we present a multi-bit encoder and FM0/Miller decoder design which has less error-rate and more security. We take resource reused, no-gap-link between different data areas of encoder, and low power into consideration in our design. FM0/Miller decoder can handle a ± 25% data rate variation and the error-rate is 0. Under TSMC 0.18μm process, the area of encoder is 27685μm² and the power is 253μw. The area of decoder is 53827μm² and the power is 394μw.

An integrated development environment for reconfigurable operators array

In this paper, an integrated development environment (IDE), which is used to map application into a target reconfigurable operators (ReOps) array, is presented. Having as input APU RTL description of an application, the IDE produces the configuration bitstream. The proposed IDE supports a variety of ReOps array through revising the architecture file which including the definition of ReOps, interconnection segments and connection switches, as well as the scale of array and organization of ReOps. A set of benchmarks is given to verify the flow of proposed IDE.

A universal framework of dual-use model for both performance and functionality based on the abstract state machine

Confronted with ever increasing design complexity, modeling system architectures for early performance evaluation and fast exploration of the design space will be a necessary process. Meanwhile, function verification has been a bottleneck for time to market. The sharing of the two processes will greatly enhance the efficiency of system development. This paper presents a universal framework of dual-use model for both performance and functionality based on the abstract state machine, to reuse the performance model in building reference model to reduce the cycle of verification. The Application Program Interface (API) function library based on Universal Verification Methodology (UVM), corresponding to the dual-use model, is provided simultaneously. Associated with the function library, the abstract state machine is recorded by the state machine component in Verification Expert System (VES) toolbox to generate specific code automatically.

Dataflow driven hardware description method and its circuit synthesis based on operators

To simplify the design & verification complexity and speed up design, a data flow driven hardware description method and its circuit synthesis based on operators are proposed. The behavior of each data is described precisely using a high level abstract language which is quite similar to ANSI C. The compilation tool ReCom compiles data flow driven description into circuit based on operators. There are four kinds of operators to implement circuit, and each operator has the attribution of self-synchronization by using handshake protocol to exchange data. A FFT design is given. Compared with the design using current design methodology, its speed is faster but with a loss of area.

A full-featured Verification Intellectual Property and its application in GJB RFID protocol

This paper proposes a full-featured Verification Intellectual Property (VIP) which can be used in functional verification at transaction level. The VIP includes a gold testcase set, a hierarchical testbench and a functional model. Firstly, the natural language specification is quantified and converted to the structured specification models. Secondly, the models are transformed into the codes of testcase generator, coverage collector, and reference model simultaneously by the templates. The mappings in the two processes ensure the completeness, the traceability and the learnability of the verification resource. Through the VIP produced by this methodology, the efficiency of modeling and debugging was improved. And its application in GJB RFID protocol at 800/900MHz guaranteed that the taped out succeeded.

Design and realization of UHF RFID reader digital baseband

This paper presents an ASIC design and implementation of digital baseband system for UHF RFID reader supporting the ISO18000-6C protocol. The digital baseband consists of five parts: digital baseband receiver, digital baseband transmitter, controller, CRC (Cyclic Redundancy Check) and serial interface modules. We present a new more secure and effective encode algorithm, TPP (Truncated Pulse Position encoding), which develops from PIE (Pulse Interval Encoding). In addition, we improve the signal adjuster of the digital baseband receiver and transmitter for decoding and encoding more exactly. Under 0.18μm CMOS process, the area of reader digital baseband is 3032802μm2 and the power is 105.215mw.

A high level synthesis method for Reconfigurable Operator Array

With the complexity of IC design increasing, it becomes an emergent issue to reduce the cost and short time-t o-market of design. In this paper, we propose a high-level synthesis method for Reconfigurable Operator Array. The high-level synthesis compiler ReCom is proposed to synthesize the high-level abstract description to low-level hardware description. Meantime, three languages are proposed to implement synthesis efficiently. To prove the advantage of this method, we chose the 2 dimension 8bit s DCT algorithm as an example which consumes 1500 operators, and the sum of configuration information is 5446bits, the number of APU C code line is 29, which is much less than 389 in verilog.