Xinan Wang

Low-power hardware implementation of ECC processor suitable for low-cost RFID tags

RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper we propose a novel ALU architecture for ECC processor on tags. By specially restructured the conventional mathematical expressions of Montgomery algorithm, the ALU operation of point multiplication in our design is reduced by nearly 47%. Also, various multipliers, such as bit-serial multiplier, digit-serial multiplier and the divided algorithm are adopted to balance between power consumption and speed. To attain ultra low power consumption, other techniques, such as finite state machines (FSM) optimization, clock gating, pipelining operations and low-power target library are used in the design. The area of the ECC processor is equal to 16.9 k gates equivalents. It performs an elliptic curve point multiplication in 36174 clock cycles and has a power consumption of 6.607 ¿W at 1.28 MHz using TSMC 0.18 ¿m low-voltage cell library.

Design of FFT processor with low power complex multiplier for OFDM-based high-speed wireless applications

We introduce a fixed-point 16-bit 64-point FFT processor for OFDM-based wireless applications. The processor is based on decimation-in-time (DIT) radix-2 butterfly FFT algorithm. The canonical signed digit is used to implement constant complex multiplications with carry save add (CSA) tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDM-based high-speed wireless applications.

A 64-bit lookahead carry chain in Inverted-Domino logic

Here we present a novel 64-bit adder carry chain design implemented in Inverted-Domino (iDomino) logic that is an improved style over conventional Domino for better performance. In the proposed scheme capacitances at output node are reduced and foot transistor in Domino logic is absorbed into clock tree to increase circuit speed. A 64-bit lookahead carry chain is constructed and HSPICE simulation in 0.25 /spl mu/m CMOS parameter shows that carry propagation can be done in less than 480 ps and a 20% speed enhancement over Domino is achieved.

A 8 th -order Chebyshev Gm-C lowpass filter for DVB-H tuner

A 8th-order Chebyshev Gm-C lowpass filter for the digital video broadcasting-handheld (DVB-H) tuner is fabricated in 0.18 ¿m RF CMOS process. The filter implements lowpass transfer function with tunable cutoff frequency in the range of 3 MHz to 4 MHz. The HD3 is about -59 dB and the stop-band attenuation at 5.25 MHz is better than 29 dB. The current consumption of the filter is 4.2 mA, and the automatic tuning circuits consume the current of 1.55 mA with 1.8 V supply.

A low power 1D-DCT processor for MPEG-targeted real-time applications

A 1D-DCT processor with parallel pipelined VLSI architecture is designed for MPEG visual and audio applications. The processor is based on distributed arithmetic to obtain low power and high computation efficiency. The simulation with EDA software shows that the pipelined parallel architecture can reach an efficient compromise between hardware cost and computing speed for real-time MPEG-related applications.

The design of an IEEE802.11 WLAN hardware MAC

The design of an IEEE802.11 WLAN hardware MAC is presented in this paper. The function of WLAN MAC layer is partitioned between hardware and software. Timing-critical and low-level functions are implemented by the hardware MAC.

A single-chip CMOS UHF RFID Reader transceiver for mobile applications

A UHF RFID Reader Transceiver for China standard (840∼925 MHz) as well as meeting the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000–6C is presented. To suppress the large self-jammer from transmitter to receiver, an on-chip self-jammer cancellation (SC) circuits and a fully-integrated DC-offset Cancellation (DCOC) circuits with quickly time-varying cut-off frequency are proposed to kill the self-jammer within 15 µs. Furthermore, a mixer with capacitor cross-coupled (CCC) common-gate input stage and vertical NPN BJT switching stage is proposed to achieve high linearity (−8 dBm P1dB), good wideband matching and low 1/f noise corner. The transmitter integrated with a CMOS class-AB PA of 22 dBm output power in linear mode with 35% PAE, which is suitable for mobile applications, supports the DSB/SSB/PR-ASK modulation schemes and achieves ACPR1 of −45 dBc and ACPR2 of −60 dBc, which satisfies the stringent spectral mask of China local requirements. A sigma-delta PLL with a single LC VCO is also implemented for 250 kHz channel hopping and good phase noise (−126 dBc/Hz at 1MHz offset). The receiver has a sensitivity of down to −77 dBm in the presence of 20 dBm PA output power. The single-chip is implemented in standard 0.18 µm CMOS process. It occupies 13.5 mm2 silicon areas, and consumes 113 mA (without PA) from 1.8V supply voltage.

SW/HW co-design of a Java-based ASIP for pervasive computing in mobile applications

A 32-bit Java-based ASIP (Application Specified Instruction set Processor) is designed for pervasive computing in mobile applications to run MIPS-compatible local instructions and some application-specific Java bytecodes in a RISC-like architecture. In Java-mode, some Java bytecodes employed in the specific application are decoded into local instructions by VLSI implementation. With VHDL simulation tools, SW/spl bsol/HW co-design verified that Java bytecodes could be executed on the processor with a local thread for a real-time visual processing. Furthermore, the design was synthesized to physical layout according to 1.2 /spl mu/m standard CMOS technology and the simulation shows that the processor can run at a frequency of 20 MHz.

VLSI implementation of fast Fourier transformation for OFDM-based high-speed wireless applications

In this paper, we introduce a fixed-point 16-bit 64 point FFT processor architecture for OFDM-based wireless applications. The processor is based on the DIT (decimation-in-time) radix-2 butterfly FFT algorithm. A canonical signed digit is used to implement constant complex multiplications with a CSA tree for lower power and cost. The simulation shows the module can reach low cost/spl bsol/power and high speed for OFDM-based high-speed wireless applications.

Software/hardware co-design of a Java-based 32bit microprocessor for mobile multimedia applications

A 32bit Java-based processor is designed for mobile multimedia applications to run MIPS-compatible local instructions and some application-specific Java bytecodes in a RISC-like architecture. In Java-mode, some Java bytecodes employed in the specific application are decoded into local instructions by VLSI implementation. With VHDL simulation tools, SW/HW co-design verified that Java bytecodes could be executed on the processor with a local thread for a real-time visual processing. Furthermore, the design was synthesized to physical layout according to 1.2 /spl mu/m standard CMOS technology and the simulation shows that the processor can run at a frequency of 20 MHz.