Shaodi Gao

On continuous Homotopic one layer routing

We give an &Ogr;(n<supscrpt>3</supscrpt>·log n) time and &Ogr;(n<supscrpt>3</supscrpt>) space algorithm for the continuous homotopic one layer routing problem. The main contribution is an extension of the sweep paradigm to a universal cover space of the plane.

Channel routing of multiterminal nets

This paper presents a new algorithm for channel routing of multiterminal nets. We first transform any multiterminal problem of density d to a socalled extended simple channel routing problem (ESCRP ) of density 3d/2+O(√dlog d), which will then be solved with channel width w ≤3d/2+O(√dlog d) in the knock-knee model. The same strategy can be used for routing in the other two models: The channel width is w ≤ 3d/2+O(√dlog d)+O(f) in the Manhattan model, where f is the flux of the problem, and w ≤ 3d/2+O(√dlogd) in the unit-vertical-overlap model. In all three cases we improve the best known upper bounds.

Advances in homotopic layout compaction

Homotopic compaction is the compaction of a VLSI layout by means of a continuous motion of layout components that preserves routability. We present the most efficient algorithm for one-dimensional homotopic compaction yet discovered: it requires timeO(oN 2 log N) and space O(N 2) on input of size N. These bounds are pessimistic, and practical performance may be close to linear. Our algorithm generates the complete constraint system for a layout and can therefore be adapted to perform wire length minimization as well as automatic jog insertion. It applies to layered circuits under rectilinear wiring rules, and also to knock-knee layouts, for which no efficient compaction algorithm was previously known. 1. Homotopic Compaction A powerful approach to the physical design of VLSI layouts is to consider wires as flexible connections with fixed topology. From this homotopic viewpoint, there is a natural one-dimensional compaction problem that may be stated as follows [13]. Call a layout routable if it can be made legal by deforming its wires in some continuous fashion that preserves the layout topology. Given a routable layout, we wish to find a layout of minimum width reachable by a continuous motion of modules and wires that displaces each module horizontally, maintains the connections between wires and modules, and preserves routability. An algorithm for this problem can perform layout compaction with optimal automatic jog insertion, even if wires are not restricted to Manhattan geometry. This paper presents an algorithm for onedimensional homotopic compaction that substantially Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee a n d / o r specific permission.

On Steiner Minimal Trees in Grid Graphs and Its Application to VLSI Routing

In this paper we present an algorithm for Steiner minimal trees in grid graphs with all terminals located on the boundary of the graph. The algorithm runs in O(k2*mink2 log k, n) time, where k and n are the numbers of terminals and vertices of the graph, respectively. It can handle non-convex boundaries and is the fastest known for this case. We also describe a new approach to the homotopic routing problem in VLSI layout design, which applies our Steiner tree algorithm to construct minimum-length wires for multi-terminal nets.

AN ALGORITHM FOR STEINER TREES IN GRID GRAPHS AND ITS APPLICATION TO HOMOTOPIC ROUTING

In this paper we present an algorithm for Steiner minimal trees in grid graphs with all terminals located on the boundary of the graph. The algorithm runs in O(min{k4, k2n}) time, where k and n are the numbers of terminals and vertices of the graph, respectively. It can handle non-convex boundaries and is the fastest known for this case. We also consider the homotopic routing problem and apply our Steiner tree algorithm to construct minimum-length wires for multi-terminal nets.

Parallel hierarchical global routing for general cell layout

In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine and experiment results on different examples show relative speedup between 4 and 5 for 8 processors. The speedup is achieved without compromising the quality of the routing results.

On Continuous Homotopic One Layer Routing

We give an O(n3 · log n) time and O(n3) space algorithm for the continuous homotopic one layer routing problem. The main contribution is an extension of the sweep paradigm to a universal cover space of the plane.