Wolfgang Rülling

On continuous Homotopic one layer routing

We give an &Ogr;(n<supscrpt>3</supscrpt>·log n) time and &Ogr;(n<supscrpt>3</supscrpt>) space algorithm for the continuous homotopic one layer routing problem. The main contribution is an extension of the sweep paradigm to a universal cover space of the plane.

Compaction on the torus

In this paper we introduce a general framework for com- paction on a torus. This problem comes up whenever an array of iden- tical cells has to be compacted. We instantiate our framework with several specific compaction algorithms: one-dimensional compaction without and with automatic jog insertion and two-dimensional com- paction.

Exact accumulation of floating-point numbers

The authors present a new idea for designing a chip which computes the exact sum of arbitrarily many floating-point numbers, i.e. it can accumulate the floating-point numbers without cancellation. Such a chip is needed to provide a fast implementation of Kulisch arithmetic. This is a new theory of floating-point arithmetic which makes it possible to compute least significant bit accurate solutions to even ill-conditioned numerical problems. The proposed approach avoids the disadvantages of previously suggested designs which are too large, too slow, or consume too much power. The crucial point is a technique for a fast carry resolution in a long accumulator. It can also be implemented in software. >The authors present a new idea for designing a chip which computes the exact sum of arbitrarily many floating-point numbers, i.e. it can accumulate the floating-point numbers without cancellation. Such a chip is needed to provide a fast implementation of Kulisch arithmetic. This is a new theory of floating-point arithmetic which makes it possible to compute least significant bit accurate solutions to even ill-conditioned numerical problems. The proposed approach avoids the disadvantages of previously suggested designs which are too large, too slow, or consume too much power. The crucial point is a technique for a fast carry resolution in a long accumulator. It can also be implemented in software.<<ETX>>

Compaction on the torus (VLSI layout)

A compacter takes as input a VLSI layout and produces as output an equivalent layout of smaller area. An effective compaction system frees the designer from the details of the design rules, and hence, increases his or her productivity and on the other hand produces high quality layouts. A general framework for compaction on a torus is introduced. This problem comes up whenever an array of identical cells has to compacted. The framework is instantiated by several specific compaction algorithms: one-dimensional compaction without and with automatic job insertion and two-dimensional compaction. >

A new method for hierarchical compaction (VLSI)

A framework for the compaction of hierarchically specified layout sketches is proposed. The main advantage of the method is that it maintains the layout hierarchy. Thus, the produced output has the same efficient representation as the input and further efficient processing of the layout becomes possible. >

A circuit for exact summation of floating-point numbers

In recent years methods for solving numerical problems have been developed which in contrast to traditional numerical methods compute intervals which are proven to contain the true solution of the given problem (cf. [10,11]). These methods rely on an exact evaluation of inner product expressions in order to obtain good (i.e. small) enclosure intervals. Practical experience has shown that using these methods even ill conditioned problems can often be solved with maximum accuracy. Since the exact inner product computation is a basic operation for these methods we developed a circuit to support the difficult part of the inner product computation: the accurate accumulation of the partial products.

On Continuous Homotopic One Layer Routing

We give an O(n3 · log n) time and O(n3) space algorithm for the continuous homotopic one layer routing problem. The main contribution is an extension of the sweep paradigm to a universal cover space of the plane.

A generalized topological sorting problem

Motivated by an application in the design of VLSI layouts, we consider a generalization of the usual topological sorting problem on directed, acyclic graphs. The difference is that an instance of the generalized problem may require some nodes in the graph to occupy fixed positions in the topological order. We also allow several nodes to share the same position in the topological order.