Shaofeng Guo

Impacts of Random Telegraph Noise (RTN) on Digital Circuits

Random telegraph noise (RTN) is one of the important dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac trap effects of RTN in digital circuits and their impacts on circuit performance are systematically investigated. Instead of trap occupancy probability under dc bias condition (pdc), which is traditionally used for RTN characterization, ac trap occupancy probability (pac), i.e., the effective percentage of time trap being occupied under ac bias condition, is proposed and evaluated analytically to investigate the dynamic trapping/detrapping behavior of RTN. A simulation approach that fully integrates the dynamic properties of ac trap effects is presented for accurate simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure probabilities of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on pac. The results show that degradations are highly workload dependent and that pac is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are helpful for robust and resilient circuit design.

A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology.

New insights into the design for end-of-life variability of NBTI in scaled high-κ/metal-gate Technology for the nano-reliability era

In this paper, a new methodology for the assessment of end-of-life variability of NBTI is proposed for the first time. By introducing the concept of characteristic failure probability, the uncertainty in the predicted 10-year VDD is addressed. Based on this, variability resulted from NBTI degradation at end of life under specific VDD is extensively studied with a novel characterization technique. With the further circuit level analysis based on this new methodology, the timing margin can be relaxed. The new methodology has also been extended to FinFET in this work. The wide applicability of this methodology is helpful to future reliability/variability-aware circuit design in nano-CMOS technology.

New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits

In this paper, the statistical characteristics of complex RTN (both DC and AC) are experimentally studied for the first time, rather than limited case-by-case studies. It is found that, over 50% of RTN-states predicted by conventional theory are lost in actual complex RTN statistics. Based on the mechanisms of non-negligible trap interactions, new models are proposed, which successfully interpret this state-loss behavior, as well as the different complex RTN characteristics in SiON and high-κ devices. The circuit-level study also indicates that, predicting circuit stability would have large errors if not taking into account the trap interactions and RTN state-loss. The results are helpful for the robust circuit design against RTN.

New observations on complex RTN in scaled high-κ/metal-gate MOSFETs — The role of defect coupling under DC/AC condition

The coupling effect between multi-traps in complex RTN is experimentally studied in scaled high-κ/metal-gate MOSFETs for the first time. By using extended STR method, the narrow “test window” of complex RTN is successfully expanded to full VG swing. Evident defect coupling can be observed in both RTN amplitude and time constants. Interesting nonmonotonic bias-dependence of defect coupling is found, which is due to two competitive mechanisms of Coulomb repulsion and channel percolation conduction. The decreased defect coupling is observed with increasing AC frequency. Based on the new observations on complex RTN, its impacts on the circuit stability are also evaluated, which show an underestimation of the transient performance if not considering defect coupling. The results are helpful for future robust circuit design against RTN.

Impacts of metastable defect states on gate oxide trapping in nanoscale MOS devices

In this paper, a modified 4-state trap model (4SM) is proposed and adopted in practical simulations including measurement delays, which can well explain the different frequency dependences of single oxide trapping and AC NBTI observed in experiments. The results also indicate the most probable activation energy of high-κ gate oxide traps, which is helpful for deep understanding of the physical origin and the impact of trapping/detrapping in nanoscale MOS devices under different frequencies.

Understanding NBTI-induced dynamic variability in the nano-reliability Era: From devices to circuits

This paper gives a brief overview of our recent findings on the NBTI-induced dynamic variations during device/circuit aging.

On the origin of frequency dependence of single-trap induced degradation in AC NBTI

The frequency dependence of the single-trap induced degradation (STID) are investigated both experimentally and theoretically, which is the key for the understanding of AC NBTI characteristics and temporal variations. Instead of the conventional 2-state trap model (2SM), the 4-state trap model (4SM) are studied through Monte-Carlo simulation in detail, which give a reasonable interpretation of the abnormal experimental results. A simple physical model is also proposed for the frequency dependence prediction, which agrees well with the simulation and experiments. This work is helpful for the evaluation of the impact of AC NBTI under different frequencies.

DTMOS mode as an effective solution of RTN suppression for robust device/circuit co-design

In this paper, using DTMOS as an effective solution of RTN suppression without device/circuit performance penalty is proposed and demonstrated for the first time, with experimental verification and circuit analysis. The experiments show that RTN amplitude is greatly reduced in DTMOS mode, which is even better than the body-biasing technique of FBB, due to the efficient dynamic modulation mechanism. Circuit stability and performance degradation induced by RTN are much improved in the design using DTMOS. New characteristics of RTN physics in DTMOS are also observed and studied in detail. The results are helpful to the robust and reliable device/circuit co-design in future nano-CMOS technology.

Investigation on the amplitude distribution of random telegraph noise (RTN) in nanoscale MOS devices

In this paper, the amplitude (ΔId/Id) distribution of random telegraph noise (RTN) induced by each trap in nanoscale devices is investigated based on the statistical experimental results. The RTN states are extracted through the proposed Gaussian mixture model (GMM). Mont-Carlo simulation is performed to extract the most probable results for mean trap number and each RTN amplitude. The results show that the RTN amplitude distribution is well consistent with the lognormal distribution instead of the exponential distribution for both the DC and AC results, which is helpful for future robust digital circuit design against RTN.