Shen Huajun

Influences of high-temperature annealing on atomic layer deposited Al2O3/4H-SiC

High-temperature annealing of the atomic layer deposition (ALD) of Al2O3 films on 4H-SiC in O2 atmosphere is studied with temperature ranging from 800 °C to 1000 °C. It is observed that the surface morphology of Al2O3 films annealed at 800 °C and 900 °C is pretty good, while the surface of the sample annealed at 1000 °C becomes bumpy. Grazing incidence X-ray diffraction (GIXRD) measurements demonstrate that the as-grown films are amorphous and begin to crystallize at 900 °C. Furthermore, C—V measurements exhibit improved interface characterization after annealing, especially for samples annealed at 900 °C and 1000 °C. It is indicated that high-temperature annealing in O2 atmosphere can improve the interface of Al2O3/SiC and annealing at 900 °C would be an optimum condition for surface morphology, dielectric quality, and interface states.

Improved adhesion and interface ohmic contact on n-type 4H-SiC substrate by using Ni/Ti/Ni

The Ni/Ti/Ni multilayer ohmic contact properties on a 4H-SiC substrate and improved adhesion with the Ti/Au overlayer have been investigated. The best specific contact resistivity of 3.16 × 10−5 Ωcm2 was obtained at 1050 °C. Compared with Ni/SiC ohmic contact, the adhesion between Ni/Ti/Ni/SiC and the Ti/Au overlayer was greatly improved and the physical mechanism under this behavior was analyzed by using Raman spectroscopy and X-ray energy dispersive spectroscopy (EDS) measurement. It is shown that a Ti-carbide and Ni-silicide compound exist at the surface and there is no graphitic carbon at the surface of the Ni/Ti/Ni structure by Raman spectroscopy, while a large amount of graphitic carbon appears at the surface of the Ni/SiC structure, which results in its bad adhesion. Moreover, the interface of the Ni/Ti/Ni/SiC is improved compared to the interface of Ni/SiC.

A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT

A 6 GHz voltage controlled oscillator (VCO) optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance (Neg-R) method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of -122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.

Charge trapping behavior and its origin in Al2O3/SiC MIS system

Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage (C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope (XPS) and transmission electron microscope (TEM) measurements. In addition, Rutherford back scattering (RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.

Effect of annealing on the characteristics of Ti/Al ohmic contacts to p-Type 4H-SiC

Ti/Al contacts deposited on p-type epilayer doped with Al at 2×1019 cm-3 are reported. The current-voltage curves of Ti/Al contacts annealed at different temperatures from 800 to 1000 °C were measured, which provided the specific contact resistances (SCRs) of 6.59×10-5 Ω/cm2 and 7.81×10-5Ω/cm2 after annealing at 900°C for 5min and 950°C for 2min, respectively. The microstructures of Ti/Al contact on P-type 4H–SiC were investigated by X-ray diffraction (XRD). The results of XRD show that the phases of Ti3SiC2 was formed at the metal/SiC interface after annealing, which could be effective to ohmic contacts on P-type 4H-SiC. The quantitative phase analysis were also discussed, which show that the phase composition of Ti3SiC2is key factor for low resistance to P-type 4H–SiC. Moreover, simulations proved that the gradual Ti3SiC2ISL reduces or eliminates the effective barrier height at the metal/Ti3SiC2/p-type and may also contribute to low contact resistivity.

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors*

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17 μm in thickness with 5 × 1015 cm−3 n-type doping, and the channel length is 1 μm. The MOSFETs show a peak mobility of 17 cm2/Vs and a typical threshold voltage of 3 V. The active area of 0.028 cm2 delivers a forward drain current of 7 A at VGS = 22 V and VDS = 15 V. The specific on-resistance (Ron,sp) is 18 mΩcm2 at VGS = 22 V and the blocking voltage is 1975 V (IDS < 100 nA) at VGS = 0 V.

Compact 2×2 Multi-Mode Interference Couplers with Uneven Splitting-Ratios Based on Silicon Nanowires

Two types of uneven splitting-ratio 2×2 multi-mode interference (MMI) couplers based on silicon nanowires are designed, fabricated and characterized. The splitting ratios are 85:15 and 72:28, respectively. The devices have compact sizes and low excess losses. The footprints of the rectangular MMI region are only about 3μm×18μm and 3μm×14μm, and the minimum excess losses (ELs) are 1.30 dB and 0.82 dB. The measured splitting-ratios are consistent with the designed values. Based on their performance, these 2×2 MMI couplers are suitable candidates for the coupling section of microring resonators where a large resonance bandwidth is required for high speed signal processing. The uneven splitting capability also provides a convenient way to further optimize the Q factor and the bandwidth of the resonator.

Design consideration of the thermal and electro stability of multi-finger HBTs based on different device structures

The thermal and electro stability of multi-finger heterojunction bipolar transistors (HBTs) with different structures were analyzed and discussed simultaneously. The thermal stability of the devices with different layout structures was assessed by the DC-IV test and thermal resistance calculation. Their electro stability was assessed by the calculation of the stability factor K based on the S parameter of the HBT. It is found that HBTs with higher thermal stability are prone to lower electro stability. The trade-off relationship between the two types of stability was explained and discussed by using a compact K-factor analytic formula which is derived from the small signal equivalent circuit model of HBT. The electro stability of the device with a thermal ballasting resistor was also discussed, based on the analytic formula.

Intrinsic stability of an HBT based on a small signal equivalent circuit model

Intrinsic stability of the heterojunction bipolar transistor (HBT) was analyzed and discussed based on a small signal equivalent circuit model. The stability factor of the HBT device was derived based on a compact T-type small signal equivalent circuit model of the HBT. The effect of the mainly small signal model parameters of the HBT on the stability of the HBT was thoroughly examined. The discipline of parameter optimum to improve the intrinsic stability of the HBT was achieved. The theoretic analysis results of the stability were also used to explain the experimental results of the stability of the HBT and they were verified by the experimental results.

A 10 GHz high-efficiency and low phase-noise negative-resistance oscillator optimized with a virtual loop model

A virtual loop model was built by the transmission analysis with virtual ground method to assist the negative-resistance oscillator design, providing more perspectives on output power and phase-noise optimization. In this work, the virtual loop described the original circuit successfully and the optimizations were effective. A 10 GHz high-efficiency low phase-noise oscillator utilizing an InGaP/GaAs HBT was achieved. The 10.028 GHz oscillator delivered an output power of over 15 dBm with a phase-noise of lower than –107 dBc/Hz at 100 kHz offset. The efficiency of DC to RF transformation was 35%. The results led to a good oscillator figure of merit of –188 dBc/Hz. The measurement results agreed well with those of the simulations.