Shi-Jie Wen

SRAM Interleaving Distance Selection With a Soft Error Failure Model

The significance of multiple cell upsets (MCUs) is revealed by sharing the soft-error test results in three major technologies, 90 nm, 65 nm, and 45 nm. The effectiveness of single-bit error correction (SEC) codes can be maximized in mitigating MCU errors when used together with the interleaving structure in memory designs. The model proposed in this paper provides failure probability to probabilistically demonstrate the benefits of various interleaving scheme selections for the memories with SEC. Grouped events such as MCU are taken into account in the proposed model by using the compound Poisson process. As a result of the proposed model, designers can perform predictive analysis of their design choices of interleaving schemes. The model successfully showed the difference in failure probability for different choices of interleaving schemes. The model behaved as the upper bound for failure probability when compared to the neutron test data with the 45-nm static-random-access memory (SRAM) design.

Muon-Induced Single Event Upsets in Deep-Submicron Technology

Experimental data are presented that show low-energy muons are able to cause single event upsets in 65 nm, 45 nm, and 40 nm CMOS SRAMs. Energy deposition measurements using a surface barrier detector are presented to characterize the kinetic energy spectra produced by the M20B surface muon beam at TRIUMF. A Geant4 application is used to simulate the beam and estimate the energy spectra incident on the memories. Results indicate that the sensitivity to this mechanism will increase for scaled technologies.

Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals

Ternary content addressable memory (TCAM) is more susceptible to soft errors than static random access memory (SRAM). The large di/dt issue during comparison operation reduces operating voltage ranges, which in turn reduces soft error immunity. The tight structural coupling of TCAM comparison circuits and memory cells does not allow for an interleaving design scheme in mitigating soft errors. Regular scrubbing of stored content can greatly mitigate the reliability issue caused by soft errors. However, frequent scrubbing can also affect device performance. The scrubbing interval should be determined to facilitate both reliability and performance. This paper proposes a novel, model-based approach that includes both single-bit upsets (SBUs) and multi-cell upsets (MCUs) to determine the scrubbing interval by predictive and probabilistic failure rate analysis. This model uses the compound Poisson (CP) process to count clustered random events, which are common phenomena of soft errors in technologies that use chips under 90 nm. The 20 M TCAM with 90-nm CMOS technology was tested with 180-MeV neutron strikes. The scrubbing interval determined based on the proposed model is applied to the TCAM test results. The failure probabilities based on the CP model showed 31% overestimation on average compared to the same from the test data. Such overestimation is mainly due to the independent upset assumption in the proposed model and can enable use of the model as worst case analysis. The worst case comparison with the test data showed 1.7% overestimation, which can tell the proposed model is effective in predicting upper-bound soft error reliability.

Effects of scaling on muon-induced soft errors

Experimental results are presented that indicate technology scaling increases the sensitivity of microelectronics to soft errors from low-energy muons. Results are presented for 65, 55, 45, and 40 nm bulk CMOS SRAM test arrays. Simulations suggest an increasing role of muons in the soft error rate for smaller technologies.

Effects of multi-node charge collection in flip-flop designs at advanced technology nodes

Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due to multi-node charge collection from single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment with Monte-Carlo simulations of charge generation in several technology generations.

Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS

In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design trade-offs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the transient performance and metastability robustness, and device level simulations were performed to quantify the soft-error robustness. The flip-flops were fabricated in the TSMC 40 nm process and radiation measurements were performed at several test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with a reference D flip-flop and a DICE flip-flop.

Design for Soft Error Resiliency in Internet Core Routers

This paper describes the modeling, analysis and verification methods used to achieve a reliability target set for transient outages in equipment used to build the backbone routing infrastructure of the Internet. We focus on the ASIC design and analysis techniques that were undertaken to achieve the targeted behavior using 65 nm technology. Considerable attention was paid to Single Event Upset in flip-flops and their potential to produce network impacting events that are not systematically detected and controlled. Using random fault injection in large scale RTL simulations, and slack time distributions from static timing analysis, estimates of functional and temporal soft error masking effects were applied to a system soft error model to drive decisions on interventions such as the use of larger resilient flip-flops, parity protection of registers groupings, and designed responses to detected upsets.

Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance

Interleaving, together with single error correction codes (SEC), are common techniques to protect memories against multiple cell upsets (MCUs). This kind of errors is increasingly important as technology scales, becoming a prominent effect, and therefore greatly affecting the reliability of memories. Ideally, the interleaving distance (ID) should be chosen as the maximum expected MCU size. In this way, all errors in an MCU would occur in different logical words, thus being correctable by the SEC codes. However, the use of large interleaving distances usually results in an area increase and a more complex design of memories. In this paper, the selection of the optimal interleaving distance is explored, keeping the area overhead and complexity as low as possible, without compromising memory reliability.

Thermal neutron soft error rate for SRAMS in the 90NM–45NM technology range

The thermal neutron soft error rate (SER) was measured systematically on SRAM cells in the technology range of 90nm to 45nm. We report here a substantial SER sensitivity with neutron energies below 0.4eV for many SRAM cells.

Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs

In this paper, we present HCS - Heterogeneous CRAM Scrubbing - for FPGAs. By utilizing stochastic fault modeling for SEUs in CRAM, we present a quantitative estimate of system MTTF improvement through CRAM scrubbing. HCS then leverages the fact that different SEUs have unequal effects on the circuit system operation, and thus the CRAM bits can be scrubbed at different rates based on the sensitivity of the bits to the circuit system failures. To maximize the improvement on system MTTF for a given circuit system, we present a dynamic programming algorithm which solves the problem efficiently and effectively. Through a detailed case study on system level study by an H.264/AVC decoder implemented on a Xilinx Virtex-5 FPGA, we show an estimation of 60% MTTF improvement by HCS over the existing homogeneous CRAM scrubbing method, while contributing virtually no area, performance and power overhead to the system.