Shi Longxing

A sub-circuit MOSFET model with a wide temperature range including cryogenic temperature

A sub-circuit SPICE model of a MOSFET for low temperature operation is presented. Two resistors are introduced for the freeze-out effect, and the explicit behavioral models are developed for them. The model can be used in a wide temperature range covering both cryogenic temperature and regular temperatures.

Active quenching circuit for a InGaAs single-photon avalanche diode

We present a novel gated operation active quenching circuit (AQC). In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I–V characteristic measurement results of the detector. The circuit integrated with aROIC (readout integrated circuit) is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications.

A novel trajectory prediction control for proximate time-optimal digital control DC—DC converters

The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC—DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC—DC with the proposed prediction is about 8 μs when the load current changes from 0.6 to 0.1 A.

Research into charge pumping method technique for hot-carrier degradation measurement of LDMOS

A measuring technique based on the CP (charge pumping) method for hot-carrier degradation measurement of high voltage N-LDMOS is researched in depth. The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail. At the same time, the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed. The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.

A complete BIST scheme for ADC linearity testing

In this paper, we presented algorithms for testing gain error, offset error, differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC), and proposed an easily integrated built-in self-test (BIST) scheme on chip, which has been designed using Chartered 0.35 /spl mu/m technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.

Domain strategy and coverage metric for validation

An innovative domain strategy and coverage metric for integrated circuit design validation is proposed. The domain strategy generates test points to examine the borders of a domain to detect whether a design fault has occurred, as either one or more of these borders have shifted or else the corresponding predicate relational operator has changed. The domain coverage metric is applied to measure the completeness and quality of the validation approach. The domain strategy and coverage metric have been implemented using VPI (Verilog procedural interface) and have been applied to validation of industry circuits under design. Our domain coverage tool works smoothly with simulator and vector generator. The results showed that the domain strategy is efficient in generating test points, and the domain coverage metric is powerful in finding potential boundary faults.

Domain fault model and coverage metric for SoC verification

An innovative domain fault and coverage metric for SoC verification is proposed. The domain fault model is based on a geometrical analysis of the domain boundary and takes advantage of the fact that points on or near the boundary are most sensitive to domain errors. The purpose of this paper is to present an efficient fault model and coverage metric for measuring the completeness and quality of verification approach. The domain coverage metric has been implemented using VPI (Verilog procedural interface) and has been applied to verification of SoC (system on chip) design. Our domain coverage tool works smoothly with the simulator and vector generator. The results showed that the domain fault model is accurate and efficient, the domain coverage metric is powerful at finding the potential control path boundary faults.

An advanced C programming course for the embedded systems development

C programming courses in the first or second year of college focus on basic C syntax rather than difficulties and basic skills in a real embedded systems project. An advanced C programming language course has been developed at Southeast University for senior undergraduate or graduate students to fill the gap between typical introductory courses or self-learning and the real project needs. The course organization and main topics as well as the result analysis of pre-course and after-course surveys are discussed. The comparison between the results of surveys indicates that the course organization and topics are effective and helpful for students.

A digital prediction algorithm for a single-phase boost PFC

A novel digital control algorithm for digital control power factor correction is presented, which is called the prediction algorithm and has a feature of a higher PF (power factor) with lower total harmonic distortion, and a faster dynamic response with the change of the input voltage or load current. For a certain system, based on the current system state parameters, the prediction algorithm can estimate the track of the output voltage and the inductor current at the next switching cycle and get a set of optimized control sequences to perfectly track the trajectory of input voltage. The proposed prediction algorithm is verified at different conditions, and computer simulation and experimental results under multi-situations confirm the effectiveness of the prediction algorithm. Under the circumstances that the input voltage is in the range of 90-265 V and the load current in the range of 20%-100%, the PF value is larger than 0.998. The startup and the recovery times respectively are about 0.1 s and 0.02 s without overshoot. The experimental results also verify the validity of the proposed method.

Energy-optimal dynamic voltage scaling for sporadic tasks

Reducing power consumption is a challenge to system designers. Dynamic power management (DPM) and dynamic voltage scaling (DVS) have emerged as efficient solutions to reduce the power consumption of embedded and portable systems. This paper proposes an online dynamic voltage scaling policy expressed as energy-optimal sporadic task scheduling (EOSTS) for sporadic tasks. EOSTS differs from other existing DVS policies in the fact that the former essentially consists of an energy-optimal model, based on strict theorems proving. Four theorems are proposed in this paper altogether, which is helpful to power management policy optimization research. Experimental results demonstrate that EOSTS policy is superior in power saving to general DPM policies