Qian Qinsong

A noise immunity improved level shift structure for a 600 V HVIC

A novel level shift circuit featuring with high dV/dt noise immunity and improved negative VS capacity is proposed in this paper. Compared with the conventional structure, the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt. In addition, a differential noise cancellation circuit is proposed to enhance the noise immunity further. Meanwhile, the negative VS capacity is improved by unifying the detected reference voltage and the logic blocks threshold voltage. A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics.

Process optimization of a deep trench isolation structure for high voltage SOI devices

The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15–20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundrys 0.5-μm HV SOI technology.

Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress

The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power transistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obviously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments.

Research into charge pumping method technique for hot-carrier degradation measurement of LDMOS

A measuring technique based on the CP (charge pumping) method for hot-carrier degradation measurement of high voltage N-LDMOS is researched in depth. The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail. At the same time, the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed. The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.

Layout and process hot carrier optimization of HV-nLEDMOS transistor

Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.

Thermal characteristics investigation of high voltage grounded gate-LDMOS under ESD stress conditions

The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators. The total heat and lattice temperature distributions along the Si-SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail. The influence of structure parameters on peak lattice temperature is also discussed, which is useful for designers to optimize the parameters of LDMSO for better ESD performance.

Bulk silicon CDMOS technology for an advanced PDP data drvier IC

In this paper, the 2nd LEDMOS devices based on bulk silicon(BS) process for an advanced PDP data driver IC have been developed. Not only the on-state characteristics, but also the reliabilities of 2nd LEDMOS transistors such as hot carrier effect, Kirk effect issues are improved against the 1st LEDMOS. The devices can be realized by shrinking the cell size and partly changing the structure of the devices. And by applying the 2nd LEDMOS to the new PDP Driver IC, we have succeeded in reducing the die size of the IC to about 70% comparing with that of 1st one, but its number of output stages is increased by 1.33 times and the power dissipation of the new IC is reduced by more than 15% too.