Shi Wei Ricky Lee

Dynamic penetration of graphite/epoxy laminates impacted by a blunt-ended projectile

Abstract The dynamic penetration of graphite/epoxy laminates as a result of impact by a blunt-ended projectile is investigated in the present study. The ballistic limit is determined by a series of high-velocity impact tests. A dynamic finite element analysis is performed to simulate the penetration process in composite laminates. A previously developed static penetration model is incorporated into the analysis to predict the ballistic limit. The ballistic characteristics are represented by the relationship between the striking and residual velocities of the projectile. Good agreement between experimental data and computational results implies that the ballistic limit of graphite/epoxy laminates can be predicted by the present analysis without performing dynamic impact tests.

Experimental investigations and model study of moisture behaviors in polymeric materials

In the present study, several experiments were performed to investigate the fundamental characteristics of moisture behaviors in various polymer materials and the interactions of water molecules with polymer matrix. Moisture weight gain tests were performed with different packaging materials. Both Fickian and non-Fickian diffusion behaviors were observed. The mold compound under investigation showed stronger non-Fickian absorption kinetics than the underfill. For most polymer materials in electronics packaging, saturated moisture concentration does not depend on temperature but relative humidity only as long as the temperature is far below the glass transition temperature. However, the saturated moisture content may increase significantly with temperature when the temperature is across the glass transition temperature. There are two distinct diffusion mechanisms involved in the transport of moisture: transfer across surface and transfer through bulk. Water sorption appears to be different from moisture sorption. Hydrophobic film can prevent water liquid molecules from penetrating through the surface. However, this has never been effective for the water vapor transmission through hydrophobic materials. Further in this study, mercury intrusion method was introduced to characterize the pore size and porosity of various materials. For most polymer materials, the free volume or pore sizes are in nano-meter range though the free volume fraction is usually in the range of 1% to 5%. Significant voiding can be developed at reflow process for soft films. An approximate estimation of free volume fraction using weight gain data was proposed. Furthermore, the moire interferometry technique was employed to study the aging effect of hygroscopic swelling. It was found that hygroscopic swelling is coupled with viscoelastic deformation. At last the mathematical descriptions of moisture phase transition with temperature and the governing equations for a deforming polymer with moisture effect are presented in this paper.

Effects of underfill material properties on the reliability of solder bumped flip chip on board with imperfect underfill encapsulants

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five different combinations of coefficient of thermal expansion (CTE) and Youngs modulus with the aforementioned delaminations were investigated. A fracture mechanics approach was employed for computational analysis. The strain energy release rate at the crack tip and the maximum accumulated equivalent plastic strain in the solder bumps of all cases were evaluated as indices of reliability. Besides, mechanical shear tests were performed to characterize the shear strength at the underfill-solder mask interface and the underfill-chip passivation interface. The main objective of the present study is to achieve a better understanding in the thermo-mechanical behavior of flip chip on board (FCOB) assemblies with imperfect underfill encapsulants.

High-Speed Solder Ball Shear and Pull Tests vs. Board Level Mechanical Drop Tests: Correlation of Failure Mode and Loading Speed

This study compares high-speed bondtesting (shear and pull) with board level drop testing (BLDT) of BGA packages using Sn4.0%Ag0.5%Cu solder balls and either an ENIG or OSP package substrate surface finish. High-speed shear and pull testing were carried out at various speeds; failure modes were recorded, together with force and fracture energy data. In addition, detailed microscopic analysis (SEM and EDX) was executed on both complementary surfaces (ball and pad) of brittle fracture failures from both shear and pull test samples. The results of these studies showed close similarity to those from brittle fractures generated during BLDT of the same packages. Furthermore, there was strong correlation between various bondtesting parameters at which brittle fractures occurred and the number of drops to failure seen in BLDT. In summary, it is suggested that brittle fractures obtained in high-speed bondtesting are a strong indicator of BLDT behavior.

Modeling and analysis of 96.5Sn-3.5Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board

In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on microvia buildup printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. The lead-free solder considered is 96.5Sn-3.5Ag. The 62Sn-2Ag-36Pb solder is also considered to establish a baseline. These two solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, shear creep strain history, and creep strain density range at the corner solder joint are presented for a better understanding of the thermal-mechanical behavior of the lead-free solder bumped WLCSP on microvia buildup PCB assemblies.

A quasi-static penetration model for composite laminates

A quasi-static model was developed to simulate the penetration process of composite lammates. The penetrator was blunt-ended. A series of static punch tests were conducted to characterize the load-displacement relation during penetration. The damage mechanisms were identified by DIB enhanced X-radiography and microscopic observation on sectioned specimens. The major damage modes were found to be delamination and plugging. An axisymmetric finite element analysis was performed to simulate the penetra tion process. An effective modulus scheme was adopted in the present analysis. Compari son of punch curves showed good agreement between testing and modeling.

Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer.

Investigation of IMC thickness effect on the lead-free solder ball attachment strength: comparison between ball shear test and cold bump pull test results

Ball pull test has emerged to be an attractive alternative to the traditional ball shear method for characterizing the attachment strength of solder interconnection. Since it is a relatively new development, so far there is not industrial standard to regulate this testing method. This paper discusses the effect of IMC growth after soldering and thermal aging at 150 degC. The attachment strength of solder balls with thermal aging is investigated by ball shear and cold bump pull (CBP) tests. The test configuration and the experimental data are reported in detail. The test results indicate that the CBP test method can reveal the brittle failure of solder joints with a higher sensitivity, especially under the fast pulling speed. As a result, the effect of IMC growth can be identified more easily. In addition to the correlation between the IMC thickness and the solder ball attachment strength, the micro-structure of IMC and the failure modes were discussed as well

3D stacked flip chip packaging with through silicon vias and copper plating or conductive adhesive filling

Three dimensional packaging is emerging as the solution for microelectronics development toward system on chip (SOC) and system in package (SIP). 3D flip chip structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. In this study, a prototype of 3D stacked flip chip packaging with TSVs is designed and fabricated. Fundamental techniques for this prototype fabrication are studied and discussed in detail. The formation of TSVs is by the deep reactive ion etching (DRIE) process and the plugging of TSVs may be done by either copper plating or conductive adhesive dispensing. In addition to the conceptual design, all wafer level processes are described and the subsequent die stacking assembly is also presented in this paper.

Multistack flip chip 3D packaging with copper plated through-silicon vertical interconnection

3D packaging (3DP) is an emerging trend as a solution for microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. In this study, a prototype of multistack flip chip 3D packaging with TSVs for interconnection is designed and fabricated. Processing techniques for prototype fabrication are studied and discussed in details. The formation of TSVs is by the deep reactive ion etching (DRIE) process and the plugging of TSVs is by copper plating. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented in this paper