Chao-Wen Tzeng

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

In this paper, we propose a parameterized digitally controlled oscillator that can produce oscillating-clock signal with the tunable frequency covering an entire designated range. Moreover, we formulate the all-digital phase-locked loop optimization process as a search problem, during which we can find a good configuration that not only meets the user-defined requirement but also achieves a smaller area and lower power consumption than a typical manual design. The silicon measurement results show that this is indeed a promising new alternative for analog phase-locked loops, especially for advanced nanometer technologies.

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain

In this brief, we present a robust new paradigm for diagnosing a scan chain with multiple faults that could have different fault types. As compared to previous methods, the major advantage of ours is the ability to not only target mixed multiple types of timing faults in the same scan chain but also tolerate non-ideal conditions, e.g., when these faults only manifest themselves intermittently. Unlike the previous matching-based algorithms, we formulate the diagnosis problem as an image recovery process featuring a dynamic windowing technique and a running sequence handling technique. Experimental results on a number of real designs show that this paradigm can successfully deal with some situations beyond existing methods.

A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains

Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failure is presented in this paper. As compared to previous methods, the major advantage of ours is the ability to tolerate non-ideal conditions, e.g., under the presence of certain core logic faults or for those faults that manifest themselves intermittently. We first formulate the diagnosis problem as a delay insertion process. Then, two algorithms including a greedy algorithm and a so-called best-alignment based algorithm will be proposed. Experimental results on a number of real designs are presented to demonstrate its effectiveness.

QC-fill: an X-fill method for quick-and-cool scan test

In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-Fill, built upon the existing multicasting scan architecture, can coexist with most low-capture-power (LCP) X-fill methods through a multicasting-driven X-fill method incorporating a clique-stripping scheme. QC-Fill is independent of the ATPG patterns and does not require any area-overhead since it can directly operate on an existing scan architecture incorporating test compression.

Robust paradigm for diagnosing hold-time faults in scan chains

Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failure is presented in this paper. As compared to previous methods, the major advantage of ours is the ability to tolerate non-ideal conditions, e.g., under the presence of certain core logic faults or for those faults that manifest themselves intermittently. We first formulate the diagnosis problem as a delay insertion process. Then, two algorithms including a greedy algorithm and a so-called best-alignment based algorithm are proposed. Experimental results on a number of real designs are presented to demonstrate its effectiveness

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous range, and thereby reduce the jitter significantly. This scheme incorporates a new mirror-DCO-based calibration scheme to take into account process variations. We validate this scheme by test chips in 0.18-μm CMOS technology. Measurement results show that, when operating at 1 GHz, the rms jitter is 4.3 ps (0.43%UI) and the peak-to-peak jitter is 35.6 ps (3.56%UI), respectively.

A fully cell-based design for timing measurement of memory

This work presents a scheme for measuring the timing parameters of a memorys I/O interface — including the setup/hold time and access time. For setup/hold time measurement, we incorporate a procedure that successively adjusts the timing relation between the clock signal and a controllable valid timing window to estimate the setup/hold time. For access time measurement, we propose a circuit that can capture the worst-case access time of an entire Built-In Self-Test (BIST) session as a pulse width, which is then further measured by traditional time-to-digital converter (TDC). Instead of just reporting a digital code, we also propose a calibration scheme so that we can report not just some digital codes, but also their corresponding absolute values. All the design can be constructed by standard cells. We have implemented it in TSMC 0.18nm CMOS process technology. Simulation results show that the setup time error is less than 3%, the hold time error is 7.5%, and the access time error is 4.4%, with about 6.2% area overhead when the memory size is 4096×64.

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches have been proposed in the past. The existing methods, however, suffer from one common drawback—that is, they rely on fault models and matching heuristics to locate the faults. Such a paradigm may run into difficulty when the fault under diagnosis does not match the fault model exactly, for example, when there is a bridging between a flip-flop and a logic cell, or the fault is temporal and only manifests itself intermittently. In light of this, we propose in this article a more versatile model-free paradigm for locating the faulty flip-flops in a scan chain, incorporating a number of signal processing techniques, such as filtering and edge detection. These techniques performed on the test responses of the failing chip under diagnosis directly can effectively reveal the fault location(s) in a scan chain. As compared to the previous works, our approach is better capable of handling intermittent faults and bridging faults, even under nonideal conditions, for example, when the core logic is also faulty. Experimental results on several real designs indicate that this approach can indeed catch some nasty faults that previous methods could not catch.

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects

Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be generated on the chip by embedding an All-Digital Phase-Locked Loop (ADPLL) into the circuit under test (CUT). Instead of measuring the exact propagation delay associated with each test pattern like previous time-consuming failing frequency signature based analysis [14], we test only up to three different test clock frequencies for each test pattern to provide the benefit of fast characterization, and thereby making it suitable for volume production test. We have successfully demonstrated the AF-test on an in-house wireless test platform called HOY system using fabricated chips. This method can not only detect small delay defects effectively but also provide a grading scheme for those marginal chips that might have the reliability problem.

Cell-Based Process Resilient Multiphase Clock Generation

Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness.