Shigeki Imai

Nitric acid oxidation of silicon at ∼120°C to form 3.5-nm SiO2∕Si structure with good electrical characteristics

3.5-nm-thick SiO2 layers can be formed at 120 °C by immersion of Si in 40 wt % nitric acid (HNO3) followed by immersion in an azeotropic mixture (i.e., 68 wt % HNO3). The former immersion produces a 1.1-nm SiO2 layer with a low atomic density of 2.19×1022∕cm2, where the layer acts as a catalyst for the decomposition of HNO3. The latter immersion results in a 3.5-nm SiO2 layer with a higher atomic density of 2.22×1022∕cm2. When the postmetalization annealing treatment at 250 °C in hydrogen is performed on the ⟨Al∕3.5-nmSiO2∕Si(100)⟩ metal-oxide semiconductor diodes, interface states are passivated and a low leakage current density (e.g., 8×10−4A∕cm2 at the forward gate bias of 1.5 V) is achieved.

1.5-V-Operation Ultralow Power Circuit of Poly-Si TFTs Fabricated Using the NAOS Method

We have fabricated thin-film transistors (TFTs) and liquid-crystal displays (LCDs) with monolithic drivers on glass substrates and achieved ultralow power consumption by operating with a low power-supply voltage at 3 V. The gate insulator of the TFTs has a stack structure with an ultrathin interfacial SiO2 layer formed by nitric acid oxidation of silicon and a 40-nm-thick SiO2 layer formed by plasma-enhanced chemical vapor deposition. Owing to the TFTs with the thin gate insulator, the driving circuits of the LCDs can be operated at a supply voltage of 1.5 V, which is much lower than that of conventional LCDs of 10-15 V.

Submicrometer Ultralow-Power TFT With 1.8 nm NAOS

We have fabricated submicrometer ultralow-power thin-film transistors (TFTs) with stack gate dielectric structure formed by the nitric acid oxidation of Si (NAOS) method. A 1.8 nm NAOS SiO2 layer effectively blocks the leakage current, and consequently, the thickness of a gate oxide layer deposited on the NAOS SiO2 layer can be made as thin as 20 nm. Because of the thin gate oxide layer, submicrometer TFTs with gate length in the range of 0.6-0.9 μm can be fabricated. The operation voltage of the TFTs can be set as low as 1.5 V because of the low threshold voltages (i.e., -0.6 V for P-ch TFT and 0.6 V for N-ch TFT). The drain current versus source-drain voltage curves possess an ideal feature with sufficiently high saturation currents even at 1.5 V operation voltage. The drain current versus gate voltage curves show a sharp current increase, and the subthreshold swing value is ~80 mV/dec for both P-ch and N-ch TFTs. The on/off ratio is ~109 for both P-ch and N-ch TFTs, and the channel mobility is ~100 cm2/V·s for P-ch TFT and ~200 cm2/V·s for N-ch TFT.

\hbox{SiO}_{2}/\hbox{20} \ \hbox{nm}

We have fabricated a thin-film transistor (TFT) in which a gate oxide layer possesses a stack structure with an ultrathin interfacial SiO2 layer formed by the nitric acid oxidation of silicon (NAOS) method at room temperature and a 40 nm CVD SiO2 layer. The drain current-voltage characteristics show that TFT with NAOS interfacial layer can be operated at 3 V (the conventional operation voltage is 12-15 V), indicating that a vast decrease in TFT power consumption is possible. The threshold voltage becomes less than 1 V, and the short-channel effect can be avoided.

CVD

This paper describes a highly versatile “System LCD” which has been developed for mobile applications. A key feature of the display is a multi-format capability to enable both the color depth and the spatial resolution to be dynamically controlled according to the application. This advanced functionality is realized by integrating a novel source-driver, binary-driver and clock-generator onto the panel. A 3.7″ LCD with three principal display formats has been successfully fabricated using low temperature CG-Silicon technology. The power consumption in each format has been measured at 14mW for VGA/Full-color, 8mW for QVGA/Full-color and 2mW for QVGA/Monochrome. We believe this versatile display technology, which combines both high performance and low power consumption, will be essential for the next generation of mobile products.

\hbox{SiO}_{2}

— To understand actual viewing conditions at home is important for TV design. And the preferred luminance level of LCD TVs under actual viewing conditions is also important in order to obtain both good picture quality and low power consumption. The actual viewing conditions of households and the preferred luminance levels was investigated. In a field test of 83 households, the display luminance, screen illuminance, and viewing locations were measured on site. In laboratory experiments, young and elderly subjects adjusted the luminance of an LCD-TV screen to their preferred levels under different screen illuminance levels, angular screen sizes, and average luminance levels (ALL) of the images. As a result, two equations, which represent the preferred luminance level of LCD-TV screens corresponding to different viewing conditions for young and elderly subjects were obtained. When the ALL of the images was 25% and the screen illuminance and angular screen size were set at 100 lx and 20°, respectively, the preferred luminance was 1 60 cd/m2 for the young subjects and 248 cd/m2 for the elderly subjects. By using the setting of the preferred luminance of an LCD TV under actual viewing conditions, it is possible to conserve energy consumption.

Gate Stack Structure

Electrical characteristics and physical properties of 8–10 nm silicon dioxide (SiO2) films formed on Si (100) substrates by use of the nitric acid oxidation of Si method at ∼120 °C have been investigated. The atomic density of the SiO2 layer increases with the HNO3 concentration. Fourier transformed infrared absorption measurements show that the higher the HNO3 concentration, the higher the atomic density of the SiO2 layer. From the Fowler–Nordheim plots, the barrier height at the SiO2/Si interface is found to increase with the HNO3 concentration. The leakage current density flowing through the SiO2 layer decreases with the HNO3 concentration employed for the SiO2 formation. It is concluded that the higher atomic density leads to SiO2 band-gap widening and thus to the higher band discontinuity energy at the SiO2/Si interface, which in turn results in a decrease in the tunneling probability of charge carries through SiO2. The density of oxide fixed charges decreases with an increase in the HNO3 concentrati...

Ultralow-Power TFT With Gate Oxide Fabricated by Nitric Acid Oxidation Method

Plasma-enhanced chemical vapor deposition was used to deposit layers of tetraethylorthosilicate at different temperatures. In the case of low-temperature deposition (300°C), the deposited film surface was smooth and the major surface defects of the polycrystalline silicon (poly-silicon) film surface were grooves of grain boundaries. In contrast, in the case of high-temperature deposition (500°C), the deposited silicon oxide surface exhibited hillocks, and these hillocks were derived from the top end of inclined silicon (111) where protruding nanotwin lamellae penetrated the poly-silicon thin film. The observed hillocks stemming from nanotwin lamellae could have been formed by compressive stress during high-temperature silicon dioxide deposition.

22.2: Multi‐Resolution for Low Power Mobile AMLCD

The preferred luminance level of LCD televisions under actual viewing conditions is important to obtain both good picture quality and low power consumption. We investigated actual viewing conditions of households and preferred luminance levels. As a result, we obtained equations which represent the preferred luminance level corresponding to different viewing conditions.

Survey of actual viewing conditions at home and appropriate luminance of LCD-TV screens

We have succeeded in fabrication of ultra-low power poly-Si based thin film transistors (TFTs) with 10 nm gate insulators and 1 V driving voltage. An ultrathin interfacial SiO<inf>2</inf> layer formed in 68 wt% nitric acid (HNO<inf>3</inf>) aqueous solutions at 120°C decreases a gate leakage current by two orders of magnitude, resulting in a high on/off ratio of 10⁹.