Shigeki Morinaga

Development of an Axial Gap Motor With Amorphous Metal Cores

This paper presents a novel motor design concept that utilizes amorphous cut cores in the stator and ferrite magnets in the rotor to obtain a high-efficiency motor. This motor employs a six-pole nine-slot axial gap construction and aims to provide 90% efficiency with decreased size and low cogging torque for fan motor applications. Amorphous cut cores are applied to the stator to decrease iron loss and save motor space. Skewed magnets are employed to decrease cogging torque. Three-dimensional finite element analysis was used to analyze motor performance. In order to verify the accuracy of the design, a trial motor was constructed, and a large range of experiments was conducted to measure the motor characteristics. The results of the trial motor meet the design goals.

Noncontact magnetic torque sensor

A novel noncontact magnetic torque sensor was developed which is expected to be widely used in factory automation equipment and automobiles. The sensor has two components: two magnetic drums with a torsion bar which makes the connection between the drive shaft and the load shaft, and a magnetic sensor. In order to obtain sinusoidal outputs, the magnetic sensor has multiple magnetoresistive elements with different phase angles to one other. The angles of the magnetic drums can be calculated by using sinusoidal outputs on a microcomputer. Torque can be calculated from the torsion bar angle difference. A trial torque sensor with a maximum detection torque of 200 kg-cm was manufactured. Its resolution was +or-0.7% and it could be used at 120 degrees C. >

Development of an axial gap motor with amorphous metal cores

This paper presents a noble motor design concept that utilizes amorphous cut cores in the stator to obtain a high efficiency motor. This motor employs 6-pole, 9-slot axial gap construction and aims to provide high efficiency with small size and low cogging torque for fan motor applications. Amorphous cut cores are applied to the stator to decrease iron loss and save motor space. The magnets with distinct shapes are employed to decrease cogging torque. 3D finite element analysis was used to model and analyze motor performance. In order to verify the design concept, a trial motor was constructed and a large range experiments were conducted to measure motor characteristics.

A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming

A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.<<ETX>>

A floating point processing unit for the Gmicro CPU

This paper describes the architecture and implementation of a newly developed floating point processing unit (FPU). It was developed as a high performance 32-bit coprocessor of the 32-bit Gmicro microprocessor, which satisfies the IEEE 754 Standard for Binary Floating-Point Arithmetic.

Microprocessor Control System with I/O Processing Unit LSI for Motor Drive PWM Inverter

In order to increase the performances and decrease the size and cost of control circuits for pulsewidth modulated ( PWM) inverters, a microcomputer control system has been developed. It consists of a microcomputer and an I/O processing unit large-scale integration (LSI) to control a variable-speed motor. The microcomputer performs complicated calculations and analyses of driving conditions. The I/O processing unit LSI detects motor driving states (analog to digital convsrsion and pulse count, etc.), generates PWM pulse outputs, and protects the inverter against overcurrents and power outages. The I/O processing unit LSI functions using the command data from the microcomputer. Conversion and count data can be sent to the microcomputer from the I/O processing unit LSI. For the convenience of interfaces to the microcomputer, all-digital logic circuits are developed for the I/O processing unit LSI. For example, PWM pulse outputs are generated by comparing digital data of a carrier timer and step level of a modulation wave. Undesirable harmonic components can be reduced easily by command data from the microcomputer.