Mitsuru Watabe

A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming

A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.<<ETX>>

High Performance and Cost-Effective Electronic Controller Architecture for Powertrain Systems

Electronic controllers for powertrain systems are required to meet the demands for increased system performance and functionality at reasonable cost. It is indispensable to examine the solutions from a range of view points synthetically for cost optimization. This paper describes a cost-effective hardware and software architecture of the electronic controllers for powertrain systems. A new method for noise reduction of a switching regulator, and a low standby current wakeup solution are also discussed as further functions needed for high performance powertrain systems.

A floating point processing unit for the Gmicro CPU

This paper describes the architecture and implementation of a newly developed floating point processing unit (FPU). It was developed as a high performance 32-bit coprocessor of the 32-bit Gmicro microprocessor, which satisfies the IEEE 754 Standard for Binary Floating-Point Arithmetic.