Shigenori Shimizu

On-demand design service innovations

Offering design services for manufacturers of embedded devices has become a very important business, one in which the three leading customer requirements are time to market, integration of leading-edge technologies, and cost reduction; in short, on-demand design services. In this paper, we discuss on-demand design service innovations of several types. First, we discuss our unique field-programmable gate array (FPGA)-based system emulation tool. Although embedded systems comprise a wide range of technologies and components, some important technologies and components are common to most embedded systems. Security and communications are two of these, and we have developed offerings in these areas as well. For security, we developed scalable intellectual property macros to meet the requirements for many kinds of cryptographic circuits. These macros can satisfy specific requirements--performance, size of the silicon area, and power dissipation--for many kinds of embedded systems. For communications, we developed an autonomic network configuration tool which allows an end user to avoid the potential frustration of setting up a network connection and which also automatically performs network security tasks.

Top-1: a snoop-cache-based multiprocessor

A novel cache coherence protocol and the performance analysis of a snoop-cache-based multiprocessor, TOP-1, which is tightly coupled and has pure shared memory, are presented. TOP-1 has two 64-b buses with interleaved address access to provide a high data-transfer rate, and a large snoop cache to provide a high cache hit ratio. It also has a TOP-1 hybrid coherence protocol, which allows a write-update protocol and a write-invalidate protocol to exist simultaneously. These protocols can be dynamically changed on the fly without any coherence problem. Each processor card has a statistics unit which collects various important statistical data without any hardware overhead. An overview of the TOP-1 architecture and its concepts is presented. The authors also present the TOP-1 hybrid protocol and explain how it works. They discuss the TOP-1 protocol and its performance by comparing the write-update and write-invalidate protocols.<<ETX>>

Design choices for the TOP-1 multiprocessor workstation

A snoopy-cache-based multiprocessor workstation called TOP-1 (TOkyo research Parallel processor-1) was developed to evaluate multiprocessor architecture design choices as well as to conduct research on operating systems, compilers, and applications for multiprocessor workstations. TOP-1 is a ten-way multiprocessor using the Intel 80386TM microprocessor chip and the Weitek WTL 1167TM floating-point coprocessor chip. It is currently running under a multiprocessor version of AIX®, which was also developed at the IBiy/l Tokyo Research Laboratory. Our research interest was focused on the design of an effective snoopy cache (all caches monitor all memory-cache traffic) system and the quantitative evaluation of its performance. One of the unique aspects of the TOP-1 design is that the cache supports four different, original snoopy protocols, which may coexist in the system. To evaluate the performance, we implemented a hardware statistics monitor that gathers statistical data. This paper focuses mainly on the TOP-1 cache design—its protocol, and its evaluation by means of the statistics monitor. Besides its cache design, TOP-1 has three other unique architectural features: two independently arbitrated 64-bit buses supported by two snoopy-cache controllers per processor, a communication and interruption mechanism for notifying other processors of asynchronous events, and an efficient arbitration mechanism to allow prioritized quasi-round-robin service with distributed control. These features are also described in detail.