Shigeru Oyanagi

ExMiner: an efficient algorithm for mining top-k frequent patterns

Conventional frequent pattern mining algorithms require users to specify some minimum support threshold. If that specified-value is large, users may lose interesting information. In contrast, a small minimum support threshold results in a huge set of frequent patterns that users may not be able to screen for useful knowledge. To solve this problem and make algorithms more user-friendly, an idea of mining the k-most interesting frequent patterns has been proposed. This idea is based upon an algorithm for mining frequent patterns without a minimum support threshold, but with a k number of highest frequency patterns. In this paper, we propose an explorative mining algorithm, called ExMiner, to mine k-most interesting (i.e. top-k) frequent patterns from large scale datasets effectively and efficiently. The ExMiner is then combined with the idea of “build once mine anytime” to mine top-k frequent patterns sequentially. Experiments on both synthetic and real data show that our proposed methods are more efficient compared to the existing ones.

A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks

The communication latency of Network-on-Chip (NoC) is one of the factors that significantly impacts on the application performance on System-on-Chips. To reduce the NoC latency, we propose a low latency architecture of router, which utilizes virtual output queuing (VOQ) to shorten the processing time of a packet transfer. Based on taking advantage of VOQ in buffering, the number of pipeline stages of a packet transfer can be reduced to two stages of switch allocation and switch traversal. By speculatively implementing these stages in a parallel fashion, the router can perform a packet transfer in only one clock cycle. In addition, a multiple VOQ architecture that each input port maintains more than one queue for each output channel is also proposed for improving the throughput of router. We have implemented the proposed router on FPGA and evaluated in terms of communication latency, throughput and hardware amount. The experimental results show that in a 4x4 two-dimensional mesh network, the proposed router reduces the communication latency by 25% and cost of area by 67.3% as compared to the look-ahead speculative virtual channel router.

A Real-Time Burst Detection Method

Real-time burst detection over multiple window size is useful for analyzing data streams. Various burst detection methods have been proposed. However, they are not effective for real-time detection. This work proposes a new burst detection method that reduces computation by avoiding redundant data updates. It analyses an event on its occurrence, and detects the period where arrival frequency rises rapidly to the previous period. In addition, it reduces computation by suppressing data within a certain period even in the case of emergent increase of events. The effectiveness of the proposed method is evaluated by experiments with real data.

The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip Routers

Network-on-Chip (NoC) is an important communication infrastructure for System-on-Chips (SoCs). Designing high performance NoCs with minimized area overhead is becoming a major technical challenge. In this paper, we propose the on-the-fly virtual channel (VC) allocation for low cost high performance on-chip routers. By performing the VC allocation based on the result of switch allocation, the dependency between VC allocation and switch traversal is removed and these stages can be performed in parallel. In this manner, the pipeline of a packet transfer can be shortened in a non-speculative fashion. We have implemented the proposed router on FPGA and evaluated in terms of communication latency, throughput and hardware amount. The experimental results show that, the proposed router with on-the-fly VC allocation reduces the communication latency by 27.3%, and improves throughput by 21.4% as compared to the conventional VC router. In comparison with the look-ahead speculative router, it improves the throughput by 6.2% with 17.6% reduction of area for control logic.

Three-stage pipeline implementation for SHA2 using data forwarding

The security hash algorithm 512 (SHA-512), which is used to verify the integrity of a message, involves computation iterations on data. The huge computation delay generated in that iteration limits the entire throughput of the system, and makes it difficult to pipeline the computation. To shorten the computation time in an iteration of the main loop, we used the data forwarding method. Here we introduce an architecture that simultaneously does data computation of an iteration and data movement of the next one. Then the computations are broken into two stages for one operand and three stages for another operand. The implementation occupies 1,520 hardware slices on Xilinx Virtex-4 family FPGA chip, and achieves nearly 2.2 Gbps. Thus, the implementation achieved a better area performance rate (throughput/area) in comparison with the related work.

Mining the k-most interesting frequent patterns sequentially

Conventional frequent pattern mining algorithms require users to specify some minimum support threshold, which is not easy to identify without knowledge about the datasets in advance. This difficulty leads users to dilemma that either they may lose useful information or may not be able to screen for the interesting knowledge from huge presented frequent patterns sets. Mining top-k frequent patterns allows users to control the number of patterns to be discovered for analyzing. In this paper, we propose an optimized version of the ExMiner, called OExMiner, to mine the top-k frequent patterns from a large scale dataset efficiently and effectively. In order to improve the user-friendliness and also the performance of the system we proposed other 2 methods, extended from OExMiner, called Seq-Miner and Seq-BOMA to mine top-k frequent patterns sequentially. Experiments on both synthetic and real data show that our proposed methods are much more efficient and effective compared to the existing ones.

An Input Buffer Architecture for On-chip Routers

The design of buffers in routers influences significantly on the area overhead, energy consumption as well as overall performance of the Network on Chip (NoC). In this paper, we propose an architecture that improves buffer utilization by using a shared buffer at each input port of the router. Because the buffer utilization is more efficient, the effect of reducing buffer size on the NoC performance can be minimized as compared to the conventional buffer architecture. We have implemented the proposed buffer architecture on Virtual Output Queuing (VOQ) router, which is a low-latency router. Simulation results show that the VOQ router with the proposed buffer architecture is able to provide almost similar performance using a 50% smaller buffer as compared to the conventional VOQ router.

Mining WWW access sequence by matrix clustering

Sequence pattern mining is one of the most important methods for mining WWW access log. The Apriori algorithm is well known as a typical algorithm for sequence pattern mining. However, it suffers from inherent difficulties in finding long sequential patterns and in extracting interesting patterns among a huge amount of results. This article proposes a new method for finding generalized sequence pattern by matrix clustering. This method decomposes a sequence into a set of sequence elements, each of which corresponds to an ordered pair of items. Then matrix clustering is applied to extract a cluster of similar sequences. The resulting sequence elements are composed into a generalized sequence. Our method is evaluated with practical WWW access log, which shows that it is practically useful in finding long sequences and in presenting the generalized sequence in a graph.

The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource Hardware

Abstract Currently, 360-degree panoramic images are widely used in the various area and has attracted more attention with the increased support of panoramic movies by Youtube and Facebook. At the same time, the increasing of opensource hardware gives a large contribution for innovation of manufacturing. We challenge to develop an underwater drone which equips fisheye lens for taking the panoramic images and uses an algorithm to generate 360-degree panoramic images. This paper guides to develop an opensourced 360-degree panoramic image generation, and the generation equipped underwater-drone which is extended on a Raspberry Pi computer module. The frame is designed by OpenSCAD, the printed board is designed by MakePro. For realizing the 360-degree panoramic images, the underwater-drone equips two 235-degree fisheye lenses and uses the OpenGL ES2 to for correcting the fisheye images. The goal of this research is using the underwater-drone to investigate the lake, sea and so on. Now, we are trying to investigate the species fishes in the natural lake for helping to protect the original environment.

Combining ALU chaining with two-direction address renaming load value prediction

Instruction level parallelism is one of the basic ways of increasing the performance of current processors. ALU chaining (chain technique) and load value prediction have been proposed for improving instruction level parallelism. Specifically, ALU chaining aims to reduce data dependence. However, it cannot do this when the instruction being depended upon is load instruction. Load value prediction is an effective method for reducing load delay, but the current predictor cannot deliver a good performance because that some predictors just predict few load instructions or some predictors ‘prediction accuracy is not good. In this work, we propose a two directional address renaming load value predictor that renames load instruction addresses into a data address and a store instruction address to increase the number of predictable load instructions and improve the prediction accuracy. This method is designed for the current load value predictor. We combine the proposed load value predictor with ALU chaining to im...