Lin Meng

Ancient Asian Character Recognition for Literature Preservation and Understanding

This paper introduces a project for automatically recognizing ancient Asian characters by image processing and deep learning with the aim of preserving Asian culture. The ancient characters examined include Chinese and Indian characters, which are the most mysterious, wildly used, and historic in the ancient world, and also feature multiply types. The automatic recognition method consists of preprocessing and recognition processing. The preprocessing includes character segmentation and noise reduction, and the recognition processing has a conventional recognition and deep learning. The conventional recognition method consists of feature extraction and similarity calculation or classification, and data augmentation is a key part of the deep learning. Experimental results show that deep learning achieves a better recognition accuracy than conventional image processing. Our aim is to preserve ancient literature by digitizing it and clarifying the characters and how they change throughout history by means of accurate character recognition. We also hope to help people discover new knowledge from ancient literature.

Unlocking Potential Knowledge Hidden in Rubbing

Rubbings are among the oldest ancient literatures and potentially contain a lot of knowledge waiting to be unlocked. Constructing a rubbing database has therefore become an important research topic in terms of discovering and clarifying the potential knowledge. However, current rubbing databases are very simply, and there is no process in place for discovering the potential knowledge discovery. Moreover, the rubbing characters need to be recognized manually because there are so many different character styles and because the rubbings are in various stages of damage due to the aging process, and this takes an enormous amount of time and effort. In this work, our aim is to construct a spatiotemporal rubbing database based on multi-style Chinese character recognition using deep learning, that visualizes the spatiotemporal information in the form of a keyword of rubbing images on a map. The idea is that the potential knowledge unlocked by the keyword will help with research on historical information organization, climatic variation, disaster prediction and response, and more.

The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource Hardware

Abstract Currently, 360-degree panoramic images are widely used in the various area and has attracted more attention with the increased support of panoramic movies by Youtube and Facebook. At the same time, the increasing of opensource hardware gives a large contribution for innovation of manufacturing. We challenge to develop an underwater drone which equips fisheye lens for taking the panoramic images and uses an algorithm to generate 360-degree panoramic images. This paper guides to develop an opensourced 360-degree panoramic image generation, and the generation equipped underwater-drone which is extended on a Raspberry Pi computer module. The frame is designed by OpenSCAD, the printed board is designed by MakePro. For realizing the 360-degree panoramic images, the underwater-drone equips two 235-degree fisheye lenses and uses the OpenGL ES2 to for correcting the fisheye images. The goal of this research is using the underwater-drone to investigate the lake, sea and so on. Now, we are trying to investigate the species fishes in the natural lake for helping to protect the original environment.

Fall detection for elderly persons using a depth camera

Currently, the proportion of elderly persons is increasing all over the world, and the fall accident has become a serious problem for elderly persons, especially the elderly person who lives alone. In this paper, we proposed an algorithm for detecting dangerous situations in the living room for protecting elderly persons. In this study, we get the binary image by using depth camera, and get the outline of the binary image by canny filter. Then we detect the fall by using the output outline image. We get all the white pixels in the outline image, then we calculate the tangent vector angle of each white pixels and divide them into 15° groups. If most tangent angles are below 45°, the fall is detected. The database includes over 700 images and the experimental evaluation of experimental images demonstrates that the proposed algorithm is an effective method for detecting the fall.

A dual-mode scheduling approach for task graphs with data parallelism

This paper proposes a task scheduling algorithm for multi/many-core systems. To increase the quality of results on the low computational complexity, our algorithm uses two static priorities switched during task scheduling. In our experiments, we compared the proposed algorithm with a state-of-the-art algorithm. The experimental results show that the proposed algorithm yields shorter scheduling length than our previous research.

FPGA-based BLOB Detection Using Dual-pipelining (Abstract Only)

Binary Large OBject (BLOB) detection is utilized in various fields such as car cameras, traffic sign recognition and surveillance systems. Although labeling is an important component in BLOB detection, it is difficult to be parallelized using a look-up table (LUT) in terms of data dependency. Since BLOB detection takes a long time, recognition speed and accuracy need to be improved. This research aims to detect BLOBs as fast as possible by using dual-pipelining image processing on the FPGA. Dual-pipelining is to perform pipeline processing in parallel to the upper and lower portions of an original image after dividing it into two portions. We have to consider the timing of each module around the borderline because of the data dependency in label generation. The image processing consists of Gaussian filtering, binarization, labeling, and BLOB analysis. Generally, labeling uses a LUT to combine multiple numbers for one object into the smallest number of temporary labels. In order to simplify the labeling, the connected components of each BLOB are stored and revised just in the LUT. In our approach, a BLOB can be detected when multiple temporary labels are stored in a same entry of the LUT, thus enabling us to detect BLOBs by dual-pipelining. Although our labeling method does not revise temporary labels into a unified label, BLOBs can be detected and their numbers, areas, and centroids are correctly computed. We compared our approach with a related work, which consists of three steps: identifying the connected pixels in each row, labeling the counted pixels in different rows, computing the area and centroid. Experimental results show that the dual-pipelining system using FPGA can detect BLOBs in 0.06 ms, which is 3.92 times faster than the related work and 1.83 times faster than a single-pipelining system. The dual-pipelining system utilized 1.5% of Registers, 8.4% of LUT, 24.3% of LUT-FF pairs, 91.9% of BRAM in Virtex V. The dual-pipelining system is about twice as large as the single-pipelining system. Our approach can be applied for the other areas such as traffic sign recognition and vehicle detection.

Pipelining FPPGA-based defect detction in FPDs (abstract only)

The real-time detection of defects in Flat-Panel Displays (FPDs) is very important during the production stages. This paper describes the manner in which defects induced by bubbles are detected as fast as possible by using 4-stage image processing pipelines with 3-line buffers on a Field-Programmable Gate Array (FPGA). The image processing consists of reading a Time Delay Integration (TDI) image, Laplacian filtering, binarization, and labeling. TDI is applied to the initial image of the FPD to reduce noises induced when taking the FPD images. Laplacian filtering and binarization are used to detect the edges in the image, and labeling is used to number the objects in the image for defect detection. In the 4-stage pipelining, the first stage reads the TDI image from the Block Random Access Memory (BRAM), the second stage implements Laplacian filtering and binarization, the third stage implements labeling, and the final stage revises the labels and writes them into the BRAM. The target pixel and its eight surrounding neighbors are required during Laplacian filtering, and four neighbors are necessary during labeling. Thus, three line registers (3-line buffer) are used as a general pipeline register between two neighboring stages in our system. The pipelining system accesses these 3-line buffers and runs four image processing steps in parallel. Therefore, the system uses four different addresses to access the BRAM and the 3-line buffers. Further, to facilitate performance comparison, we implemented sequential image processing systems with 3-line buffers on FPGA and CPU software. The experiments reveal that Laplacian filtering, binarization, and labeling for FPD defect detection can be executed in less than 1 ms by using four-stage pipelining on an FPGA, which is 3.62 times faster than the sequential system and 158.7 times faster than the CPU software. The pipelining system is 28% larger as compared to the sequential system in terms of the size of the LUTs.

Combining ALU chaining with two-direction address renaming load value prediction

Instruction level parallelism is one of the basic ways of increasing the performance of current processors. ALU chaining (chain technique) and load value prediction have been proposed for improving instruction level parallelism. Specifically, ALU chaining aims to reduce data dependence. However, it cannot do this when the instruction being depended upon is load instruction. Load value prediction is an effective method for reducing load delay, but the current predictor cannot deliver a good performance because that some predictors just predict few load instructions or some predictors ‘prediction accuracy is not good. In this work, we propose a two directional address renaming load value predictor that renames load instruction addresses into a data address and a store instruction address to increase the number of predictable load instructions and improve the prediction accuracy. This method is designed for the current load value predictor. We combine the proposed load value predictor with ALU chaining to im...

Control Independence Using Dual Renaming

Modern Super scalar Processor squashes up all of wrong-path instructions when the branch prediction misses. In deeper pipelines, branch miss prediction penalty increases seriously owing to large number of squashed instructions. Exploiting control independence has been proposed for reducing this penalty. Control Independence method reuses control independent instructions (CI instructions) without squashing when branch prediction misses. Reusing CI instructions at branch miss prediction is not easy because of changing data dependency between squashed instructions and CI instructions. Conventional researches of CI architecture require complex Re-renaming mechanism, or with a limited applicability. This paper proposes a new mechanism named Dual Renaming for reusing CI instructions. It assigns two tags for each source register of CI instruction, and solves data dependency with simple mechanism when branch miss prediction is detected. The simulation result shows that Dual Renaming mechanism increases IPCs by maximum 29.52%.