Shigeru Takasaki

Logic simulation engines in Japan

A description is given of HAL II and SP, ultra-high-speed logic simulation engines for use in verifying large computer logic designs. Both use parallel processor architecture with a maximum configuration of 64 processors. The resulting simulation speed is a thousand times faster than that of conventional software logic simulators run on a mainframe. HAL II and SP, which can simulate a system with several million gates, have been used successfully in the design of large digital systems for logic simulation.<<ETX>>

HAL II: A Mixed Level Hardware Logic Simulation System

This paper describes a mixed level hardware logic simulation system, called Hardware Logic Simulator II (HAL II). This paper first shows a HAL II simulation method. Then, it overviews HAL II hardware and software system configurations, simulation mechanism and estimates system performance. The HAL II system can handle a maximum of 5.8 million gates and a high level design language FDL (Functional Description Language). Finally, it discusses system applications and results. The paper also indicates that HAL II has been successfully used.

HAL III: function level hardware logic simulation

A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven algorithms at register transfer level. HAL III is more than 10000 times faster than conventional gate-level software simulators in the case of 31 processors used. HAL III can be expanded to 127 processors. HAL III can also be used as a fault simulator. Its simulation speed can be estimated more than a hundred times faster than software simulators. HAL III has been successfully used in practical VLSI designs.<<ETX>>

Block-Level Hardware Logic Simulation Machine

This paper describes a block-level hardware logic simulation machine. This is called a Hardware Logic Simulator (HAL). This paper first shows a block-level simulation method. Then, it overviews HAL hardware and software system configurations, and the simulation mechanism, and it estimates system performance. Finally, it discusses system applications and results. The paper also indicates that HAL has been successfully used.

Testability consideration based on a test pattern length estimation

A testability evaluation method is described based on an estimated test pattern length to obtain the desired fault coverage. The test pattern length is estimated from network attributes, i.e., No. of gates, No. of signal lines, No. of inputs/outputs, etc. The proposed method begins with modeling a fault coverage curve as a function of test patterns and a curve coefficient. The curve coefficient is described as a function of network attributes based on the previous execution data. The test patterns required to obtain the desired fault coverage can be estimated in the range of upper and lower bounds. The upper and lower bounds are obtained using the interpolation method. The proposed estimation method is evaluated from the relationships between estimated patterns and actual automatic test generation patterns.