Nobuhiko Koike

HAL: A High-Speed Logic Simulation Machine

The architecture of a very-high-speed logic simulation machine (HAL), which can simulate up to one-half million gates and 2M-byte memory chips at a 5 ms clock speed, is described. This machine makes it possible to debug the total system¿CPU, main memory, cache memory and control storage¿before the actual machine is fabricated. HAL employs parallel and pipeline processing, and event-driven, block-level logic simulation. The prototype system for a 32-processor system has been constructed and is now in use as a tool for large mainframe computer development. HAL is more than a thousand times faster than existing software logic simulators.

HAL; A Block Level Hardware Logic Simulator

A special purpose hardware machine, which simulates up to one half million gates and 2M byte RAM ICs at a 5 millisecond clock speed, is described. This is accomplished with a HArdware Logic (HAL) simulator. This performance is achieved with 32 distributed special parallel processors, which utilize Block Oriented Simulation Technique. The technique promises a good cost hardware logic simulator.

NEC Cenju-3: a microprocessor-based parallel computer

Presents the design considerations, machine architecture, and parallel programming environment for the parallel machine Cenju-3, the first massively parallel processor product of NEC. Cenju-3 utilizes fast commodity RISC microprocessors (VR4400) in a distributed shared-memory arrangement and can be configured with up to 256 processing elements, connected through a multistage interconnection network. It results a compact and scalable parallel machine, with operating speeds ranging from 256 MFLOPS to a maximum of 12.8 GFLOPS. A hardware support for the interprocessor communication realizes efficient message/data transmissions among processors. Also, a programming environment (PCASE) has being developed, in order to fully utilize the Cenju-3. PCASE translates a sequential user program into its efficient parallel form with a minimum of user intervention. Preliminary results and future directions are also described.<<ETX>>

HAL II: A Mixed Level Hardware Logic Simulation System

This paper describes a mixed level hardware logic simulation system, called Hardware Logic Simulator II (HAL II). This paper first shows a HAL II simulation method. Then, it overviews HAL II hardware and software system configurations, simulation mechanism and estimates system performance. The HAL II system can handle a maximum of 5.8 million gates and a high level design language FDL (Functional Description Language). Finally, it discusses system applications and results. The paper also indicates that HAL II has been successfully used.

HAL III: function level hardware logic simulation

A function-level hardware simulator, HAL III, is described. HAL III can simulate a circuit model written by a register transfer level language FDL without translating it into gate level. It adopts parallel, pipeline, and flexible FDL evaluation architectures, and uses level sort and event-driven algorithms at register transfer level. HAL III is more than 10000 times faster than conventional gate-level software simulators in the case of 31 processors used. HAL III can be expanded to 127 processors. HAL III can also be used as a fault simulator. Its simulation speed can be estimated more than a hundred times faster than software simulators. HAL III has been successfully used in practical VLSI designs.<<ETX>>

Block-Level Hardware Logic Simulation Machine

This paper describes a block-level hardware logic simulation machine. This is called a Hardware Logic Simulator (HAL). This paper first shows a block-level simulation method. Then, it overviews HAL hardware and software system configurations, and the simulation mechanism, and it estimates system performance. Finally, it discusses system applications and results. The paper also indicates that HAL has been successfully used.

MAN-YO: Mixed level parallel logic simulation engine

MAN-YO is a special-purpose parallel computing machine being developed for logic circuit design and simulation. It uses dedicated hardware to increase the speed of gate-level simulation, and a combination of dedicated microprograms and processors for functional level simulation. Furthermore, a multiprocessor architecture, interconnected by a loop-network, is used to provide concurrent processing capability for high performance, multilevel logic simulation. Experiments were conducted to assess the performance of the functional level simulation.

A functional level simulation engine of MAN-YO: a special purpose parallel machine for logic design automation

The architecture of a proto-type functional level simulator element of a massively parallel machine (MAN-YO) designed for logic design automation is presented. At functional level, hardware systems are described in a hardware description language, FDL. The FDL description is compiled into stack oriented intermediate language instructions. Communicating with other gate level/block level/ functional level processors, each functional simulator interprets the compiled instructions and simulates various circuits using 4-value logic. In order to realize high speed processing of 4-value logic/arithmetic operations, the functional simulator utilizes low-level parallelism realized by 3 ALUs which are controlled by the different fields of a long horizontal type microinstruction. By utilizing low-level parallelism at processor level, as well as processor level parallelism, high speed execution of mixed level simulation becomes possible. The system also provides further performance enhancement by compiling often used FDL macros into microcode. This paper describes an outline of the MAN-YO (Japanese for ten thousand leaf-nodes in the processor tree), a brief description of FDL, and the architecture of the functional level simulator element (called FDLPE). A rough performance based on the current design is also described.