Shigeru Yamashita

A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips

Sample preparation, which is a front-end process to produce droplets of the desired target concentrations from input reagents, plays a pivotal role in every assay, laboratory, and application in biomedical engineering and life science. The consumption of sample/buffer/waste is usually used to evaluate the effectiveness of a sample preparation process. In this paper, for the first time, we present an optimal sample preparation algorithm based on a minimum-cost maximum-flow model. By using the proposed model, we can obtain both the optimal cost of sample and buffer usage and the waste amount even for multiple-target concentrations. Experiments demonstrate that we can consistently achieve much better results not only in the consumption of sample and buffer but also the waste amount when compared with all the state-of-the-art of the previous approaches.

On error tolerance and Engineering Change with Partially Programmable Circuits

The growing size, density and complexity of modern VLSI chips are contributing to an increase in hardware faults and design errors in the silicon, decreasing manufacturing yield and increasing the design cycle. The use of Partially Programmable Circuits (PPCs) has been recently proposed for yield enhancement with very small overhead. This new circuit structure is obtained from conventional logic by replacing some subcircuits with programmable LUTs. The present paper lays the theoretical groundwork for evaluating PPCs with Quantified Boolean Formula (QBF) satisfiability. First, QBF models are constructed to calculate the fault tolerance and design error tolerance of a PPC, namely the percentages of faults and design errors that can be masked using LUT reconfigurations. Next, zero-cost Engineering Change Order (ECO) in PPCs is investigated. QBF formulations are given for performing ECOs, and for quantifying the ECO coverage of a PPC architecture. Experimental results are presented evaluating PPCs from [1], demonstrating the applicability and accuracy of the proposed formulations.

A logic integrated optimal pin-count design for digital microfluidic biochips

Digital microfluidic biochips have become one of the most promising technologies for biomedical experiments. In modern microfluidic technology, reducing the number of independent control pins that reflects most of the fabrication cost, power consumption and reliability of a microfluidic system, is a key challenge for every digital microfluidic biochip design. However, all the previous chip designs sacrifice the optimality of the problem, and only limited reduction on the number of control pins is observed. Moreover, most existing designs cannot satisfy high-throughput demand for bioassays, and thus inapplicable in practical contexts. In this paper, we propose the first optimal pin-count design scheme for digital microfluidic biochips. By integrating a very simple combinational logic circuit into the original chip, the proposed scheme can provide high-throughput for bioassays with an information-theoretic minimum number of control pins. Furthermore, to cope with the rapid growth of the chips scale, we also propose a scalable and efficient heuristics. Experiments demonstrate that the proposed scheme can obtain much fewer number of control pins compared with the previous state-of-the-art works.

A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips

Microfluidic biochips have been recently proposed to integrate all the necessary functions for biochemical analysis. There are several types of microfluidic biochips; among them there has been a great interest in flow-based microfluidic biochips, in which the flow of liquid is manipulated using integrated microvalves. By combining several microvalves, more complex resource units such as micropumps, switches and mixers can be built. For efficient execution, the flow of liquid routes in microfluidic biochips needs to be scheduled under some resource constraints or routing constraints. The execution time of the biochemical operations depends on the binding and scheduling results. The most previously developed binding and scheduling algorithms are based on heuristics, and there has been no method to obtain optimal results. Considering the above, this paper proposes an optimal method by casting the problem to a clique problem.

An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips

Digital microfluidic biochips have become one of the most promising technologies for biomedical experiments. In modern microfluidic technology, reducing the number of independent control pins that reflects most of the fabrication cost, power consumption, and reliability of a microfluidic system, is a key challenge for every digital microfluidic biochip design. However, all the previous chip designs sacrifice the optimality of the problem, and only limited reduction on the number of control pins is observed. Moreover, most existing designs cannot satisfy high-throughput demand for bioassays, and thus inapplicable in practical contexts. In this paper, we propose the first optimal pin-count design scheme for digital microfluidic biochips. By integrating a very simple combinational logic circuit into the original chip, the proposed scheme can provide high-throughput for bioassays with an information-theoretic minimum number of control pins. Furthermore, to cope with the rapid growth of the chips scale, we also propose a scalable and efficient heuristics to reduce the number of control pins. A logic optimization technique, which can be used to reduce the complexity of the integrated combinational logic circuit, is also presented in this paper. Experiments demonstrate that the proposed scheme can obtain much fewer number of control pins compared with the previous state-of-the-art works.

On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design

With continuous decrease of device geometries in the nanoscale era of digital design, increasing importance is given to the reliability aspect of basic building blocks. In this context, this brief discusses the inherent fault tolerance capability of conventional logic gates before proceeding with the analysis of error immune property of a subset of combinational standard cells present in commercial digital libraries. The analysis has led to the following inferences: (i) Compared to complex-gate implementation, discrete-gate based realization of compound logic functions enables a mean improvement in the error resiliency metric by 68.2%, and (ii) the associated increase in area overhead for discrete-gate realizations as a trade-off for enhanced fault tolerance over complex gate implementations is found to be 51.6% on average.

Better-Than-DMR Techniques for Yield Improvement

Running data-intensive scientific workflow across multiple data centers faces massive data transfer problem which leads to low efficiency in actual workflow application for scientists. By considering data size and data dependency, we propose a k-means algorithm based initial data placement strategy that places the most related initial data sets into the same data center at workflow preparation stage. During the execution of scientific workflow, by analyzing interdependent relationship between data sets and tasks, we adopt multilevel task replication strategy to reduce volume of intermediate data transfer. The simulation results show that the proposed strategies can effectively reduce data transfer among data centers and improve performance of running data intensive scientific workflows.In this paper, we improve the performance of server-side I/O scheduling on parallel file systems by transparently including information about the applications access patterns. Server-side I/O scheduling is a valuable tool on multiapplication scenarios, where the applications spatial locality suffers from interference caused by concurrent accesses to the file system. We present AGIOS, an I/O scheduling library for parallel file systems. We guide schedulers decisions by including information about the applications future requests. This information is obtained from traces generated by the scheduler itself, without changes in application or file system. Our approach shows performance improvements under different workloads of 46.3% on average when compared to a scenario without an I/O scheduler, and of 25.1% when compared to a scheduler which does not use information about future accesses.In remote sensing applications, the traditional procedure for registering a pair of images requires the manual selection of ground control points at significant landmarks of the images. The primary drawback of this approach is that a trained expert is needed to manually select each individual ground control point in the remotely sensed images. This is very laborious and time consuming. In this paper, a new feature-based approach to automate image-to-image registration is proposed for remote sensing applications. This new approach exploits the nonsubsampled contourlet transform to automatically extract a set of control points across spatial and directional resolutions where misalignment between images can be expected to appear. Preliminary experimental results demonstrate the effectiveness and accuracy of the proposed algorithm.For improving the circuit yield, a variety of works based on Dual-Modular Redundancy (DMR) have been studied. Recently, a novel circuit model, Partially Programmable Circuit (PPC), which is made through inserting some Look-Up Tables (LUTs) in conventional logic circuits, has been also proposed. However, they have in common in that they suffer from large area overhead, especially when not all but some faults are specified to be bypassed. Focusing on the fact that an identical copy of parts of the original circuits in DMR and the full programmability of LUTs in PPCs both contain too much functionality for bypassing specified faults, in this paper, we propose three methods to efficiently reduce the functionality of sub-circuits. They can be classified into two approaches, the first one is to reduce the programmability of LUTs in PPCs, and the second one is to apply different ASIC-based sub-circuits, each of which is to bypass a single fault. For the second approach, we propose a novel framework, called Multiple Functional Redundancy (MFR) and its compression method. Experimental results demonstrated that our proposed methods overcome traditional DMR and the original PPC in area overhead while achieving the same yield improvement.

A redundant wire addition method for Patchable Accelerator

Patchable Accelerator has been recently proposed to achieve high frequency and high energy-efficiency with enabling post-silicon Engineering Change (EC). However, Patchable Accelerator suffers from too much usage of the hardware resources when an EC takes place. In addition, Patchable Accelerator needs to delay operations to deal with ECs under some specific conditions. These problems occur because of lack of wires. Therefore, we propose a heuristic method such that redundant wires are added to the most appropriate parts in a datapath. Our case study shows that our method is much quicker than a brute-force approach and its result is near optimum.