Shigeshi Abiko

A 1-V programmable DSP for wireless communications [CMOS]

In an effort to extend battery life, the manufacturers of portable consumer electronics are continually driving down the supply voltages of their systems. For example, next-generation cellular phones are expected to utilize a 1-V power supply for their digital component. To address this market, an energy-efficient, programmable digital signal processing (DSP) chip that operates from a 1-V supply has been designed, fabricated, and tested. The DSP features an instruction set and micro-architecture that are specifically targeted at wireless communication applications and that have been carefully optimized to minimize power consumption without sacrificing performance. The design utilizes a 0.35-/spl mu/m dual-V/sub t/ technology with 0.25-/spl mu/m minimum gate lengths that enables good performance at 1 V. Specifically, the chip dissipates 17 mW at 1 V, achieving 63-MHz operation with a power-performance metric of 0.21 mW/MHz.

A 1 V DSP for wireless communications

Modern cellular phones are placing increasingly stringent demands on battery life and, therefore, on the power dissipation of the embedded DSP circuitry. At the same time, greater computational throughput is being required of the DSP, for example to implement more sophisticated speech and channel coding algorithms. Earlier low-power DSPs were reported. However, further improvements in power and performance are required. This paper describes a full-function, 1.6M-transistor, fixed-point programmable DSP designed for wireless communication applications to address these dual constraints of lower power and higher throughput. This is achieved by operating at 1V and using a dual-V process to maintain high performance.