Mahalingam Nandakumar

Shallow trench isolation for advanced ULSI CMOS technologies

This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows: (a) Trenches have sidewall angle >/spl sim/80/spl deg/ to maintain trench depth and isolation at narrow space. The trench bottom is rounded to minimize stress. (b) Pad oxide undercut, prior to liner oxidation in halogen ambient or at high temperature, provides adequate corner rounding to suppress edge leakage, with minimum loss of active area. (c) HDP and TEOS-O/sub 3/ CVD oxides can fill 0.16 /spl mu/m wide trenches free of voids. Lower trench aspect ratios (thinner nitride and liner oxide, and shallower trenches), and process improvements allow scaling to smaller dimensions. Gapfill process, liner oxide, and thermal cycles are tailored to prevent stress-induced defects, trench sidewall and corner damage. (d) CMP step height uniformity is improved by using dummy active areas, nitride overlayer or patterned etchback. (e) Optimization of retrograde well and channel stop implants minimizes sensitivity of N/sup +/-P/sup +/ isolation to overlay tolerance and improves latch-up performance.

Transistor design issues in integrating analog functions with high performance digital CMOS

Pocket or halo designs used in high performance digital CMOS design can degrade analog device performance. A new understanding of this phenomenon is presented using device simulation. The effect of pocket implant parameters on the trade-off between digital and analog performance is studied experimentally. Experimental data showing the beneficial effects of eliminating the pocket selectively from the drain end on analog performance is also shown.

A 1-V programmable DSP for wireless communications [CMOS]

In an effort to extend battery life, the manufacturers of portable consumer electronics are continually driving down the supply voltages of their systems. For example, next-generation cellular phones are expected to utilize a 1-V power supply for their digital component. To address this market, an energy-efficient, programmable digital signal processing (DSP) chip that operates from a 1-V supply has been designed, fabricated, and tested. The DSP features an instruction set and micro-architecture that are specifically targeted at wireless communication applications and that have been carefully optimized to minimize power consumption without sacrificing performance. The design utilizes a 0.35-/spl mu/m dual-V/sub t/ technology with 0.25-/spl mu/m minimum gate lengths that enables good performance at 1 V. Specifically, the chip dissipates 17 mW at 1 V, achieving 63-MHz operation with a power-performance metric of 0.21 mW/MHz.

A 1 V DSP for wireless communications

Modern cellular phones are placing increasingly stringent demands on battery life and, therefore, on the power dissipation of the embedded DSP circuitry. At the same time, greater computational throughput is being required of the DSP, for example to implement more sophisticated speech and channel coding algorithms. Earlier low-power DSPs were reported. However, further improvements in power and performance are required. This paper describes a full-function, 1.6M-transistor, fixed-point programmable DSP designed for wireless communication applications to address these dual constraints of lower power and higher throughput. This is achieved by operating at 1V and using a dual-V process to maintain high performance.

An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

In this paper the effects of technology scaling on the fraction of active power P/sub a/ wasted as short-circuit power P/sub s/ are studied through SPICE simulations. The accuracy of SPICE is verified against experimental data. SPICE simulations show that lowering V/sub T/ below 0.1 V can increase P/sub s//P/sub a/ significantly beyond what is expected from increased subthreshold leakage. P/sub s//P/sub a/ is typically higher at higher V/sub cc/ but to first order P/sub s//P/sub a/ is determined by signal slew rates and V/sub T/. It is shown that the input slew rate is constrained by P/sub s//P/sub a/ at low V/sub T/ and by performance at higher V/sub T/. We show that P/sub s/ increases with increasing gate sheet resistance. A simple analytical model for this effect is verified against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa<10% for sub-0.25 /spl mu/m technologies.

A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V)

A high performance 1.5 V, sub-0.18 /spl mu/m (physical) gate length CMOS technology and extension to a 1.0 V technology for low power applications is described. nMOS with nominal I/sub drive/=740, 580, and 380 /spl mu/m are achieved for V/sub DD/=1.8, 1.5, and 1.0 V at accumulation t/sub ox/=36 A (from C-V at V/sub gb/=-3 V). pMOS with nominal I/sub drive/ of 300 (1.8 V), 222 (1.5 V), and 140 /spl mu/A//spl mu/m (1.0 V) are achieved. Target L/sub g//sup min/ (minimum gate length)=0.15-0.16 /spl mu/m. Drive currents are comparable to a recently reported 0.08 /spl mu/m CMOS process. Low nMOS R/sub SD/<220 /spl Omega/-/spl mu/m and pMOS R/sub SD/<500 /spl Omega/-/spl mu/m are achieved. Improvements to 1.5 V CMOS include CoSi/sub 2/ cladding, pocket implant for n- and pMOS, increased HDD and S/D dose with increased anneal, and low temperature backend processing <700/spl deg/C. Scaling of the 1.5 V CMOS to 1.0 V CMOS is achieved by (a) reduction of V/sub T/ implant dose or (b) use of shallow channel counterdoping (CD) if the V/sub T/ dose cannot be reduced further. With reduced V/sub T/ dose, nominal V/sub T//sup sat/ is reduced from 0.25 V (1.5 V CMOS) to 0.10 V (1.0 V CMOS) with small short-channel effect (SCE) for both designs. With CD and same pocket process from 1.5 V CMOS, low V/sub T/ devices are achieved with lower and constant V/sub t//sup sat/=0.06 V from L/sub gate/=0.25-0.25 /spl mu/m and with low SCE. Inverter chain delay of 37 psec for the 1.0 V, 36 A, 0.18 /spl mu/m CMOS is reduced 40% compared to a prior 1.0 V, 48 A, 0.25 /spl mu/m process.

Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology

This paper describes the integration of active and passive components to enable embedding analog circuits in an advanced digital CMOS technology developed for low standby power integrated circuits. Device design issues, device characteristics, and technology scaling are discussed in this context. The components include 1.5 V digital core CMOS, 1.5 V analog and 3.3 V I/O MOSFETs. In addition to these self-aligned MOSFETs we describe drain-extended transistors, DEnMOS and DEpMOS, where the drain extensions are formed using the well implants. A novel structure to improve the substrate collector, vertical pnp bipolar transistor is presented. The passive components described here are the n-poly on n-well capacitors and a polysilicon resistor with a low temperature coefficient of resistance, usually referred to as the zero-TCR resistor. The analog integration adds one extra mask used to block silicidation of the zero-TCR polysilicon resistor.

A shallow trench isolation for sub-0.13 /spl mu/m CMOS technologies

The design of a shallow trench isolation (STI) for sub-0.13 /spl mu/m CMOS technologies is described in this paper. The areas addressed and key results of the STI are as follows. (a) A deep UV lithography with a surface imaging resist can define trench openings down to 0.12 /spl mu/m with good linearity. (b) A new high density plasma (HDP) CVD oxide process is able to fill 0.16 /spl mu/m wide and 0.5 /spl mu/m deep trenches without voids and to maintain good junction leakage and charge to breakdown (Q/sub bd/). (c) Optimized Nwell/Pwell implant doses and well and channel stop (CS) implant energies are described using both experimental data and tuned device simulations. Interwell (N/sup +/-to-Nwell and P/sup +/-to-Pwell) isolation of 0.15 /spl mu/m or N/sup +/-to-P/sup +/ spacing of 0.3 /spl mu/m, and intrawell (N/sup +/-to-N/sup +/ and P/sup +/-to-P/sup +/) isolation of 0.12 /spl mu/m have been achieved. Latch-up is shown to correlate well with /spl alpha//sub NPN/+/spl alpha//sub PNP/, the sum of the common base current gains of the parasitic NPN and PNP transistors. Good latch-up (holding voltage>1.5 V) has been achieved using 0.5 /spl mu/m deep trench with optimized CS and well implant conditions.

A device design study of 0.25 /spl mu/m gate length CMOS for 1 V low power applications

A 0.25 /spl mu/m gate length CMOS with multiple-V/sub T/ is proposed for 1 V low power applications; low-V/sub T/ devices for critical paths, and high-V/sub T/ devices for the rest of the circuit. Various device designs, viz. super-steep retrograde (SSR), SSR with surface counter doping (CD), conventional, and conventional with CD, to realize the high- and low-V/sub T/ devices are experimentally evaluated by comparing the nominal I/sub DRIVE/ and V/sub T/ rolloff. It is found that the SSR+CD channel profile is optimum for low-V/sub T/ CMOS, while SSR and conventional are optimum for high-V/sub T/ NMOS and PMOS, respectively. The power and performance tradeoffs for these devices are evaluated using a verified figure-of-merit and SPICE simulations, and the results are found to be reasonably comparable to published data.

The effect of deterministic spatial variations in retrograde well implants on shallow trench isolation for sub-0.18 /spl mu/m CMOS technology

The high energy retrograde well implants for sub-0.18 microns CMOS are done at a normal or near normal incidence to minimize the shadowing due to the thick photoresist edges. The endstation geometry in a high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively impact device performance. We show that the spatial variations can have significant impact on shallow trench isolation (STI), by causing in a deterministic pattern the failure of STI devices on a wafer. These spatial variations are important and need to be taken into consideration for STI design.