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Dive into the research topics where Shigetaka Kasuga is active.

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Featured researches published by Shigetaka Kasuga.


IEEE Journal of Solid-state Circuits | 2004

1/4-inch 2-mpixel MOS image sensor with 1.75 transistors/pixel

Mitsuyoshi Mori; Motonari Katsuno; Shigetaka Kasuga; Takahiko Murata; Takumi Yamaguchi

This paper presents new MOS image sensor technologies that realize ultra-small pixel size, i.e., 2.25/spl times/2.25 /spl mu/m/sup 2/, with high sensitivity and low supply voltage. A 1/4-inch 2-Mpixel MOS image sensor has been developed by a new pixel configuration and by a new pixel design with a 0.25-/spl mu/m CMOS process. In the new pixel configuration, a unit pixel consists of one photodiode (PD), one transfer transistor, and an amplifier circuit with three transistors which are shared by four pixels. As a result, the unit pixel has 1.75 transistors. High sensitivity has been achieved by a high aperture ratio of 25%. In the new pixel design, the low supply voltage of 2.5 V has been realized by optimizing both the potential profile in the PD and the gate length of the transfer transistor.


international solid-state circuits conference | 2008

A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis

Takayoshi Yamada; Shigetaka Kasuga; Takahiko Murata; Yoshihisa Kato

In this work, we have developed an image sensor capable of shooting both dark- and bright-objects in one synthesized frame without necessitating any buffer memories. Multiply acquired signals with different exposure periods can be synthesized in each pixel, in which a feedback loop circuit is incorporated. The pixel feedback loop comprises a storage capacitor, a feedback capacitor and pass transistors. This configuration enables repetition of the image acquisition process, i.e. exposure, signal storage during the next exposure and synthesis of the successively exposed signals, as many times as needed.


IEEE Transactions on Electron Devices | 2006

A 2.0-/spl mu/m pixel pitch MOS image sensor with 1.5 transistor/pixel and an amorphous Si color filter

Masahiro Kasano; Yuichi Inaba; Mitsuyoshi Mori; Shigetaka Kasuga; Takahiko Murata; Takumi Yamaguchi

In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m design rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine design rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.


international solid-state circuits conference | 2004

A 1/4in 2M pixel CMOS image sensor with 1.75 transistor/pixel

Mitsuyoshi Mori; Motonari Katsuno; Shigetaka Kasuga; Takahiko Murata; Takumi Yamaguchi

A 2.5V CMOS image sensor using a pixel configuration of four photodiodes in one unit sharing seven transistors is presented. This image achieves a 2.25/spl mu/m pixel pitch with 25% aperture ratio in a 0.25/spl mu/m IP2M CMOS process.


international solid-state circuits conference | 2005

A 2.0 /spl mu/m pixel pitch MOS image sensor with an amorphous Si film color filter

M. Kasano; Y. Inaba; Mitsuyoshi Mori; Shigetaka Kasuga; Takahiko Murata; Takumi Yamaguchi

A CMOS image sensor with an amorphous Si film color filter is implemented on a standard Si process. The color filter thickness is less than 100 nm. The sensor achieves a 30% aperture ratio by a 1.5 transistor/pixel architecture and a 0.15 /spl mu/m design rule.


international solid-state circuits conference | 2010

A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure technique

Takeo Azuma; Taro Imagawa; Sanzo Ugawa; Yusuke Okada; Hiroyoshi Komobuchi; Motonori Ishii; Shigetaka Kasuga; Yoshihisa Kato

The recent trend in ultra-high-density cameras is running from HD to 4K2K, which will further extend to 8K4K / portable 4K2K. With advancements in device fabrication process technologies, there has been a pressing need for the miniaturization as well as high resolution and high sensitivity in image sensors [1].


international solid-state circuits conference | 2016

6.6 A 1280×720 single-photon-detecting image sensor with 100dB dynamic range using a sensitivity-boosting technique

Mitsuyoshi Mori; Yusuke Sakata; Manabu Usuda; Sejii Yamahira; Shigetaka Kasuga; Yutaka Hirose; Yoshihisa Kato; Tsuyoshi Tanaka

Continuous improvements in sensitivity have opened up applications for image sensors such as camcorders, digital still cameras, mobile phones, and surveillance cameras. Even though leading-edge image sensors have reached the noise floor of a few electrons [1,2], a thrust towards darker levels still continues down to an illumination level equivalent to being under a crescent moon (i.e., 10-2 down to 10-4 lux). This requires single-photon detection with typical digital cameras pixel size, i.e., 1.5 to 5μm. Although huge-size pixel [3] or single-photon avalanche photodiode (SPAD) based image sensors [4] have been presented for such a purpose, in general, both have to pay area and dark current penalties. Thus, an image sensor capable of both single-photon detection and normal imaging providing us with a high dynamic range is a huge technological challenge.


international electron devices meeting | 2016

An APD-CMOS image sensor toward high sensitivity and wide dynamic range

Mitsuyoshi Mori; Yusuke Sakata; Manabu Usuda; Shigetaka Kasuga; S. Yamahira; Yutaka Hirose; Yoshihisa Kato; A. Odagawa; Tsuyoshi Tanaka

We present a sensitivity-boosting technique by incorporating an avalanche photodiode into a normal photo-conversion region. Under a dark scene, an avalanche photodiode operation is selected, where the photo-electrons are multiplied up to 105 electrons. Under a bright scene, a photodiode operation is selected, where photo-electrons in proportional to light intensity are generated in a similar way to conventional CMOS image sensors. Alternating the two operations enables wide operational range extending to dark conditions.


Archive | 2011

Solid-state imaging device.

Takahiko Murata; Takumi Yamaguchi; Shigetaka Kasuga


Archive | 2006

SOLID-STATE IMAGE SENSOR AND MANUFACTURING METHOD THEREOF

Takumi Yamaguchi; Takahiko Murata; Shigetaka Kasuga

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