Shigetaka Kumashiro

Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures

An approach to computing the time response of an arbitrary 3-D interconnect structure based on asymptotic waveform evaluation (AWE) is introduced. It has been implemented in a software tool called 3DAWE. To facilitate the application of AWE to a 3D RC mesh network model, the AWE formulation is rederived based on a nodal analysis approach. The ICCG matrix solver has been successfully applied in 3DAWE. It is shown that the typical transient response of a reasonably large 3D RC network can be obtained within a few minutes on a 15-MIPS computer using this program. >

A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation

A novel memory cell has been proposed for low voltage operated, high speed and high density SRAMs. Features of this cell are (1) high performance poly-Si TFT loads utilizing bipolar action positively, and (2) a node contact structure which keeps current drivability of TFTs to the cell nodes high by the elimination of parasitic high resistance regions. The minimum operation voltage of 1.5 V has been confirmed by 0.3 /spl mu/m design rule 64 kbit SRAMs without a boosted word-line scheme.

A triangular mesh generation method suitable for the analysis of complex MOS device structures

A fully automatic triangular mesh generation method which can correctly handle the MOS inversion current along any arbitrary shaped channel is proposed. The key idea of this method is to introduce an interface protection layer which consists of rectangular mesh locally conformed to the material interface. The performance of this method is verified through an oblique and a SLIT transistors simulation.<<ETX>>

A triangular mesh with the interface protection layer suitable for the diffusion simulation

An automatic Delaunay partitioned mesh generation which is effective in reduction of numerical errors in a diffusion process near the interface or in the thin layer is proposed. An interface protection layer which consists of a rectangular mesh locally conformed to a material interface is introduced. A validity of the interface protection layer for avoiding an artificial threshold voltage shift of about 1 V due to a boron penetration through a pMOS gate oxide is demonstrated.

A new diffusion algorithm during oxidation which can handle both phosphorus pile-up and boron segregation at Si-SiO/sub 2/ interface

A new simulation algorithm during oxidation which can handle both the phosphorus (P) pile-up and the boron (B) segregation has been proposed. In this algorithm, an interlayer (IL) is placed at Si-SiO/sub 2/ interface in order to have P pile-up. The interface is moved according to the Si consumption during a time step and a new interface is generated at the end of the consumed Si region. A region between an old and a new IL is defined as a transition layer (TL). A diffusion equation is solved inside the TL using local effective diffusion constants in order to fully redistribute the impurities. By using this diffusion in the TL, the P piled up in the old IL may move through the TL and re-piles up into the new IL, and B segregation can be simulated accurately. The V/sub th/-V/sub sub/ characteristics of an actual buried channel pMOSFET which is simulated using the proposed algorithm agrees well with the experiment.

A Systematic and Physically Based Method of Extracting a Unified Parameter Set for a Point-Defect Diffusion Model

A systematic and physically based method for extracting of a unified parameter set for a point-defect diffusion model is proposed. A sensitivity matrix analysis is used to construct the sequence of the extraction and to select the data set to be fitted.

Advanced process/device modeling and its impact on the CMOS design solution

Accurate global modeling is a key issue for the successful application of TCAD to the ULSI device design solution. To demonstrate how far we can go with the state-of-the-art global modeling, we tried to design 0.13 [/spl mu/m] CMOS device by using our globally calibrated advanced process/device models. This paper reports the design methodology and the results compared with the fabricated device characteristics.

Fabrication and modeling of a novel self-Aligned AlGaAs/GaAs heterojunction bipolar transistor with a cutoff frequency of 45 GHz

This paper establishes a systematic approach for design, fabrication, and modeling of a newly proposed self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) employing a two-dimensional heterostructure device simulator and a heterojunction bipolar transistor circuit simulator. The developed HBT has an abrupt emitter-base heterojunction, and applies a novel structure in which a single base-electrode is placed between two emitter-electrodes. A fabricated 3 × 8 µm2two-emitter HBT exhibits a measured current gain cutoff frequency fT=45 GHz which is believed to be the highest, ever reported, for all kinds of bipolar transistors. Results of frequency divider circuit simulation indicate that the developed HBT would be 1.4 times faster than a conventional HBT in which one emitter-electrode is located between two base-electrodes.