Susumu Asada

Analysis of leakage current in buried heterostructure lasers with semiinsulating blocking layers

An effective device structure for reducing leakage current in buried heterostructure laser diodes with semi-insulating InP blocking layers is analyzed. The analysis utilizes a semiconductor device simulator in which deep trap levels are taken into account. It predicts that the addition of a thin wide-bandgap InGaP layer in the semi-insulating region at the mesa boundaries as a barrier to prevent double injection into the semi-insulating region is effective in reducing leakage current. >

Two-dimensional numerical analysis of lasing characteristics for self-aligned structure semiconductor lasers

Lasing characteristics in 0.78 mu m AlGaAs-GaAs self-aligned structure (SAS) lasers are calculated on the basis of a newly developed two-dimensional analytical method. The calculated results are compared in detail with experimental results for MOVPE (metalorganic vapor phase epitaxial) grown SAS lasers. It is shown that calculated results agree well with experimental results, and that the newly developed two-dimensional simulator is very effective in calculating actual lasing characteristics accurately. The optimum design conditions for AlGaAs-GaAs SAS lasers obtained from experimental and calculated results are discussed. >

Waveguiding effect on modal gain in optical waveguide devices

The waveguiding effect on modal gain in narrowly confined structures in optical waveguide devices, such as semiconductor laser diodes, is discussed. It is shown that a difference exists between the rigorous modal gain derived from the wave equation and the approximate modal gain used in the literature. This difference means that there is an enhancement of the rigorous modal gain, which depends on active region sizes. The extent of the enhancement is numerically estimated and found to be nonnegligible in standard optical waveguide devices. >

Time-Dependent Dielectric Breakdown Characterization of 90- and 65-nm-Node Cu/SiOC Interconnects with Via Plugs

As the wiring-space decreases, the time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant (k) interconnects becomes a critical reliability issue and more accurate prediction of the TDDB lifetime will be required. In this investigation, TDDB dependences on temperature and electric field are studied comprehensively for 90- and 65-nm-node Cu/SiOC interconnects using practical multilevel test structures with via plugs. Low-electric-field TDDB tests down to 1 MV/cm were carried out by a package TDDB method with high temperature up to 300 °C. Linear dependence of the TDDB lifetime on the electric-field is observed down to 1 MV/cm, and this suggests that the lifetime can be predicted using the E-model. The linear dependence of the TDDB lifetime on temperature is also observed up to 300 °C at 1.8 MV/cm. The activation energies for the 90 and 65 nm nodes are almost the same values, 0.76 eV for the 90 nm node and 0.74 eV for the 65 nm node. Failure is observed at the interfaces between the cap dielectric (SiCN) and the silicon dioxide layer with a surface polished by chemical-mechanical polishing (CMP) for both nodes. It is noted that no difference in the failure modes is seen between dense SiOC for the 90 nm node and porous SiOC for the 65 nm node, in spite of the different materials used for the intermetal dielectrics. This suggests that the polished interfaces greatly affect on the TDDB lifetime for both nodes. Improved TDDB lifetime is obtained by increasing the post-CMP cleaning time and the pretreatment time before the cap dielectric deposition. Sufficient TDDB lifetimes of over 10 years under practical operating conditions are obtained for both 90- and 65-nm-node Cu/low-k interconnects with via plugs.

A triangular mesh with the interface protection layer suitable for the diffusion simulation

An automatic Delaunay partitioned mesh generation which is effective in reduction of numerical errors in a diffusion process near the interface or in the thin layer is proposed. An interface protection layer which consists of a rectangular mesh locally conformed to a material interface is introduced. A validity of the interface protection layer for avoiding an artificial threshold voltage shift of about 1 V due to a boron penetration through a pMOS gate oxide is demonstrated.

Oxygen ion etching mechanism investigation by surface enhanced Raman scattering

Reaction products on the surface of an etched polymethylmethacrylate (PMMA) film during O2 reactive ion etching (RIE) have been studied for clarifying RIE processes. Surface enhanced Raman scattering, due to sputtered silver particles on the surface of the etched PMMA film, is used for the surface analysis. The measured Ar laser Raman spectrum for etched PMMA film exhibits double peaks at 1350 and 1580 cm−1 with a subpeak at 1780 cm−1. Judging from the observed graphite and molecular spectra, the double peaks are interpreted as being due to carbon with fused ring structure on the etched PMMA surface. The subpeak is attributed to oxidized carbon structure with C=O bond. The presence of these carbon reaction products is expected to dominate organic film etching mechanisms.