Shigeyuki Nishitani

32.2: An Innovative Pixel-Driving Scheme for 64-Level Gray-Scale Full-Color Active Matrix OLED Displays

Innovative pixel driving for active matrix OLED displays is described. A full-color display with a luminous deviation of less than 1.6%, which means a 6-bit or 64-level gray-scale accuracy, is shown. The driving is preferable for full-color video with gamma correction.

21.1: Common‐Decoder Architecture for Compact and Power‐Saving Poly‐Si Data‐Driver Circuits

We have proposed the common-decoder architecture for a data-driver circuit fabricated by using a poly-Si process: the architecture achieves a compact circuit and low power consumption. In application to a 6-bit data driver, this architecture replaces the 6-bit vertical bus lines that occupy a large area of the conventional DAC with two vertical signal lines. It also suppresses the power consumption of the data bus by reducing the number of bits inverted in word-to-word transitions from six to two. We fabricated an AMOLED panel with an integrated 6-bit data-driver circuit having 384 outputs, using a conventional 4-micron design rule. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 microns. We confirmed that the drivers maximum power consumption was only 5 mW and that the AMOLED panel showed smooth 64-level gray-scale characteristics. Furthermore, we fabricated an AMLCD panel including driver circuits of the same type as integrated elements. Six-bit full-color images were successfully displayed on both panels.

Clamped-inverter circuit architecture for luminescent-period-control driving of active-matrix OLED displays

— An innovative pixel-driving technology for high-performance active-matrix OLED flat-panel displays is described. Called “clamped-inverter circuit architecture,” it uses luminescent-period-control driving to reduce the inter-pixel non-uniformity caused by the device-to-device variability of low-temperature poly-Si TFTs. A prototype full-color display shows a luminous deviation of less than 1.6%, which corresponds to only the LSB-error in 6-bit gray-scale.

45.3: Automatic Adjustment Method of Parameters in CRT Interface Circuit for LCD Monitor

For 13.3-inches diagonal XGA Super TFT-LCD monitor with the CRT interface, we have developed automatic adjustment method of parameters in A/D conversion circuit, for example offset, gain, phase and frequency. Therefore, this TFT-LCD monitor can provide with high quality display with easy control.

Compact and power‐saving polysilicon data driver with common‐decoder DA converter (CD‐DAC)

— A common-decoder architecture for a data-driver circuit fabricated by using a polysilicon process has been developed. The architecture achieves a compact circuit and low-power consumption. In application to an integrated polysilicon data driver for small-sized displays, this architecture reduces the area of the data driver by removing the vertical bus lines that occupy a large area. It also suppresses the power consumption of the data bus by reducing the number of driven lines in the data bus during word-to-word transitions from six to two. By using a conventional 4-μm design rule, we fabricated an active-matrix OLED (AMOLED) panel with an integrated six-bit data-driver circuit with 384 outputs. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 μm. The maximum power consumption of the driver was only 5 mW, i.e., 3.8 mW for logic-data transfer and 1.2 mW for reference-voltage source. Furthermore, we also fabricated an active-matrix LCD (AMLCD) panel including driver circuits of the same type as the integrated elements. Six-bit full-color images were successfully displayed on both panels.

Development of a 15.5-in. STN-LCD monitor with CRT interface

We have developed a 15.5-in.-diagonal XGA STN-LCD monitor with a CRT interface. This STN-LCD monitor can accelerate the frame frequency in order to optimize STN-LCD driving, and realize a 260K-color display. For this monitor development, we have developed the new Dual FRC method (D-FRC), which can realize both saving of memory capacity and reducing flicker. We have optimized the display pattern of D-FRC, and minimized crosstalk by the combination of D-FRC and Hi-Addressing (Advanced 2-line simultaneous addressing).