Shih-Che Huang

Degradation of the Capacitance-Voltage Behaviors of the Low-Temperature Polysilicon TFTs under DC Stress

In this paper, the degradation of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dc stress is investigated with measurement of the capacitance between the source and the gate (C GS ), as well as the capacitance between the drain and the gate (C GD ). It is discovered that the degradation in C GD curves of the device after hot carrier stress shows apparent frequency dependence, while that in the C GS curves remains almost the same. A circuit model based on the channel resistance extracted from the current-voltage behavior is proposed to describe the frequency dependence of the capacitance behavior. From this model, it is revealed that the anomalous frequency-dependent capacitance-voltage characteristics may simply reflect the transient behaviors of the channel resistances. Besides, it was found that the C GS curves after self-heating effect exhibit a significant shift in the positive direction and an additional increase for the smaller gate voltage, while the C GD curves show only positive shifts. By employing simulation, it was proved that the self-heating effect creates interface states near the source region and increases the deep states in the poly-Si film near drain. The proposed circuit model further explains the behavior of the C GS and C GD curves for the stressed device at different measuring frequencies.

Analysis of Poly-Si TFT Degradation Under Gate Pulse Stress Using the Slicing Model

The device degradation of polycrystalline-silicon thin-film transistors stressed with different gate pulse waveforms is investigated. It is first observed that the degradation is dependent on the rising time of the gate pulses for the gate voltage swing below the threshold voltage. The degradation ratio of the mobility is analyzed with respect to two factors, namely, the magnitude of the lateral transient electric field and the change in the numbers of the carrier near the edges of the channel. A new index considering these two factors is proposed to depict the device degradation. It shows good linearity between the degradation in mobility and the proposed index

The Linear Combination Model for the Degradation of Amorphous Silicon Thin Film Transistors under Drain AC Stress

The degradation behavior of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) under steady-state (DC) and pulsed (AC) stress on drain electrode has been investigated in this paper. Signals with various peak levels, frequencies and duty ratios are applied onto the drain electrode to see their effects on devices reliability. The effects of state creation and removal are found to still be the dominant degradation mechanisms of drain stress. With the experiment data, it is significantly proved that the degradation behavior can be predicted by analyzing the gate-to-source and gate-to-drain vertical electric field during stress. Furthermore, a linear combination model has been contributed in this paper. By using this model, one can estimate the threshold voltage shift under drain AC stress of different voltage levels, frequencies, duty ratios for a given stress time. With satisfactory agreement between the real and estimated data, this model has been proved to be very useful in predicting and evaluating a-Si:H TFT reliability with both gate and drain signal applied.

A Statistical Model for Simulating the Effect of LTPS TFT Device Variation for SOP Applications

In this paper, the variation characteristics of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are investigated with a statistical approach. A special layout is proposed to investigate the device variation with respect to various devices distances. Two non-Gaussian equations are proposed to fit the device parameter distributions, whose the coefficients of determination (R2) are both near 0.9, reflecting the validity of the model. Two benchmark circuits are used to compare the difference between the proposed model and the conventional Gaussian distribution for the device parameter distribution. The output behaviors of the digital and analog circuits show that the variation in the short range would greatly affect the performance of the analog circuits and would instead be averaged in the digital circuits.

Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region

This letter reports the study of the reliability behavior of poly-Si thin-film transistors (TFTs) with the pulsed gate voltage lower than the threshold voltage. First, the equivalent circuit model for poly-Si TFT is proposed. Considering the voltage drop for each element in the circuit model during the OFF-region gate dynamic stress, it is proposed that the main voltage drop occurs at the source and drain junctions, which could in turn degrade the device during stress. Based on this assumption, the gated p-i-n device fabricated on the same glass with the identical process conditions is stressed and analyzed. The similarity between the capacitance curves of the TFTs and gated p-i-n devices after stress proves that the main reason for degradation of poly-Si TFTs under gate OFF region ac stress is the large voltage drop across the source and drain junctions.

Degradation of Capacitance-Voltage Characteristics Induced by Self-Heating Effect in Poly-Si TFTs

The degradation of poly-Si thin film transistors (TFTs) under self-heating stress was investigated via the capacitance between the source and the gate (C GS ), and that between the drain and the gate (C GD ). Consequently, the normalized C GS and C GD after stress positively shift 2 V for the gate voltage near flat band voltage. In addition, C GS raises about 40% for the lower gate voltage, while C GD raises only about 10%. With simulation results, it is found that the self-heating effect creates interface states near the source region and the deep states near drain, resulting in the different inclines of the of C GS and C GD curves.

Characterization of the Channel-Shortening Effect on P-Type Poly-Si TFTs

The phenomenon of channel shortening for p-type poly-Si thin-film transistors (TFTs) after stress is studied in this paper. Increased mobility, shifted threshold voltage V TH , and reduced leakage current for the stressed device are observed. In addition, the capacitance-voltage (C- V) behavior for the stressed device exhibits the anomalous increase for the measuring gate voltage in the OFF region. A model illustrating how the trap electron mechanism would occur is provided. Furthermore, the degradation behavior of the p-type poly-Si TFT under gate ac stress in the OFF region is also studied. Similar degradation behaviors are observed for the gate-ac-stressed TFT for both of their I-V and C-V characteristics. A distributed device circuit model is proposed, and based on this model, it is proposed that the main voltage drop during gate ac stress in the OFF region could occur at the source and drain junction, which may, in turn, degrade the device. A gated p-i-n device under the same process condition is then adopted and dc stressed to verify the proposed mechanism. The similarity between the capacitance curves for the ac-stressed TFT and the dc-stressed gated p-i-n device proves the validity of the proposed mechanism.

Generalized Hot-Carrier Degradation and Its Mechanism in Poly-Si TFTs Under DC/AC Operations

In the previous report, we had reported the mechanism for the degradation of poly-Si TFTs under OFF region gate ac operation with the source and drain electrodes grounded. In this paper, the study is extended to the degradation of the devices under various ac and dc operation conditions. It is discovered that, though these stress conditions are different, the corresponding degradation behaviors in their I-V and C-V curves all resemble the degradation behavior of the device under dc hot-carrier stress. Two important factors, namely, the electric field across the junction and the number of carriers flowing through the junction, are taken into discussion in this paper and comparison of these stress conditions. It is then categorized that these operation conditions can be described as the “generalized hot-carrier effect,” since the degradation is found to occur near the junctions by the energized carriers, just as that under dc hot-carrier stress. The qualitative comparison of the electric field and carrier flow through the junction for the four stress conditions as well as the difference in the degradation mechanism between MOSFETs and poly-Si TFTs are also provided.