Shiji Pan

Design of a CMOS On-Chip Slot Antenna With Extremely Flat Cavity at 140 GHz

A novel design for a fully on-chip antenna operating at 140 GHz that can be fabricated with standard CMOS technology is proposed. In addition to the traditional microstrip feeding, the slot antenna is backed with an extremely thin cavity formed by two CMOS inner metal layers and vias in between. The proposed cavity prevents radiation from going inside the lossy silicon substrate and enhances the radiation of the slot antenna. It is also shown that the antenna radiation is not affected significantly by other metallic parts on the chip. Good agreement is achieved between results from a frequency-domain solver, HFSS, and a time-domain solver, CST. The simulated gain is around -2 dBi, and the radiation efficiency is around 18%, despite ohmic losses enhanced by the extreme flatness. The input 10-dB bandwidth is around 5 GHz. The total area of this antenna is 1.2 × 0.6 mm2 (0.56 λ0 × 0.28 λ0 at 140 GHz).

Design and Analysis of a W-band 9-Element Imaging Array Receiver Using Spatial-Overlapping Super-Pixels in Silicon

A W-band direct-detection-based receiver array is presented using a new concept of spatial-overlapping super-pixels for millimeter-wave imaging applications in an advanced 0.18 μm BiCMOS process. The use of spatial-overlapping super-pixels results in improved SNR at the pixel level through a reduction of spillover losses, partially correlated adjacent super-pixels, a 2×2 window averaging function in the RF domain, the ability to compensate for the systematic phase delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point, and the ability to compensate for mutual coupling effects among the array elements. The receiver chip achieves a measured peak coherent responsivity of 1,150 MV/W, an incoherent responsivity of 1,000 MV/W, a minimum NEP of 0.28 fW/Hz 1/2 and a front-end 3-dB bandwidth from 87-108 GHz, while consuming 225 mW per receiver element. The measured NETD of the SiGe receiver chip is 0.45 K with a 20 ms integration time.

A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude control

Benefiting from aggressive feature size scaling, silicon technologies have recently shown the capability of implementing W-band imaging receivers with an image resolution of 1.5mm and temperature resolutions of less than 0.5K [1-4]. This paper extends the capability of an imaging array receiver by improving image resolution using the novel concept of spatial-overlapping sub-arrays and enhancing image capture time using a phased-array within an imaging array receiver (RX). Specifically, the design and implementation of a BiCMOS 9-element array RX consisting of four 2×2 overlapping sub-arrays is presented. The RF-path-sharing between neighboring sub-arrays leads to a reduction in the chip area by 40% as compared to a conventional imaging array consisting of four 2×2 non-overlapping sub-arrays, while improving the RXs spatial resolution due to the higher sub-array density. Each 2×2 sub-array in this imaging array RX forms a pixel (Fig. 8.5.1).

Investigation of a Wideband BiCMOS Fully On-Chip

Design and implementation of a W-band on-chip bowtie-shaped slot antenna fabricated in 180-nm BiCMOS process is presented, and its performance and limitations are discussed. This antenna has a measured impedance bandwidth (S11 <; -10 dB) across the W-band frequency range and a very wide gain bandwidth, making it a candidate for wideband applications. The measured gain for this antenna is 0-1 dBi at 94 GHz. This letter also analyzes the influence of the RF probe to the on-chip antenna performance.

W

The application of high impedance layer (HIL) in (Bi)CMOS millimeter wave on-chip antennas is studied. The HIL consists of grounded two-dimensional periodic dogbone-shaped elements that use a metal layer of the CMOS structure. Two different mechanisms that take advantage of the HIL in on-chip antenna design are investigated. First, we implant the HIL below the on-chip dipole antenna to act as an artificial magnetic conductor (AMC), which enhances the radiation of the dipole. We have obtained 1.2 dB realized gain for a dipole antenna placed above a 4×5 dogbone array at 90 GHz. The second use of the HIL is directly as a radiating antenna, without the need of the dipole antenna on top. In this case we have obtained −2dB accepted gain from a HIL made of 5×5 dogbone array, fed by two microstrip lines having 180° phase difference. The results are obtained by full-wave simulation.

-Band Bowtie Slot Antenna

High impedance surfaces (HISs) have been proposed and used as substrate for dipoles for realizing low-profile antennas. Here, we show that HISs can be used directly as low-profile antennas with a single feed point, without any dipole on top. The structure is made of only two metallic layers, the patterned surface and the ground plane below, at a subwavelength distance. We analyze two possible feeding mechanisms of an HIS made of dogbone-shaped conductors, though the ideas proposed here can be applied also to other HIS structures. We show that broadside gain of the order of 7-11 dBi can be obtained. We also explain that radiation of the HIS is in part related to a TM-like leaky wave with attenuation constant that is not as small in contrast to other standard high-gain leaky-wave antennas.

High impedance layer for CMOS on-chip antenna at millimeter waves

A novel fully on-chip antenna based on a metasurface fabricated in a 180-nm BiCMOS process is presented. Inspired by the concept of high impedance surface (HIS), this metasurface is not used as a reflector below an antenna as commonly done. Instead, it is used as a radiator by itself. The extremely thin metasurface is composed of a patterned top two metal layers and the ground plane placed in the lowest metal layer in the process. The ground plane on the lowest metal layer of the process provides a solid shielding from the substrate and other possible circuitries. The fundamental of the antenna radiation and design are described. The measured antenna shows -2.5 dBi peak broadside gain with 8-GHz 3-dB gain bandwidth and an impedance bandwidth larger than 10 GHz. In its class of broadside radiating fully on-chip antennas, with a ground plane on the lower metal layer of the process, and without additional fabrication processing, this structure achieves the widest impedance bandwidth at W-band and one of the highest gain and gain bandwidth. It is noteworthy that this is achieved with an extremely thin antenna substrate thickness and a shielding ground plane.

Direct Use of the High Impedance Surface as an Antenna Without Dipole on Top

This paper presents a fully planar antenna based on a metamaterial consisting of a planar array of dogbones. The unit element of this high impedance surface (HIS) is composed of a layer with dogbone shaped conductors on top of a thin dielectric substrate backed by a metal ground plane. A HIS as an intermediate-gain antenna at C band is demonstrated. Previously, HISs have been employed in order to improve the radiation performance of antennas on top of them, this yields to low profile planar antenna applications. In this paper the idea is to eliminate the antenna above the HIS and instead use the HIS itself as an antenna. The direct use of a HIS as an antenna thus allows designing even thinner antennas. The leaky wave modes supported by this kind of metalayer have been previously demonstrated, and the main principle of this HIS antenna is the excitation of such modes in the finite array of dogbones to achieve broadside radiation. Various ways of exciting this antenna are explained and radiation patterns are given as simulation results. Also antennas in various sizes are compared with respect to the broadside gain.

A 94-GHz Extremely Thin Metasurface-Based BiCMOS On-Chip Antenna

In this work, four designs of (Bi)CMOS on-chip antenna (OCA) at 90GHz and 140GHz are shown and compared, aiming at the difficult task of broadside radiation (off the top chip metal surface). A bowtie-shaped slot antenna is fabricated and expected to offer a gain of −1.5dB at 90GHz and 30GHz impedance bandwidth. Another design of slot antenna backed by a cavity, which is fully isolated from the circuits, gives a gain of −2 dB at 140GHz and 5 GHz bandwidth. Additionally, a design of a slot antenna based on an integrated waveguide in (Bi)CMOS showing −1 dB gain is proposed. At last, a proposed E-shaped patch antenna, which only occupies 0.7 mm × 0.7 mm area, shows −2 dB gain with 10 GHz bandwidth.

High impedance surface as an antenna without a dipole on top

The paper presents several feasible millimeter wave on-chip antenna designs suitable to be fabricated in CMOS technology without any additional process. The results are listed and compared with state-of-the-art designs in the literature. The difficulties in designing high efficiency antenna on CMOS chip are discussed.