Leland Gilreath

Design and Analysis of a W-Band SiGe Direct-Detection-Based Passive Imaging Receiver

A W-band direct-detection-based receiver front-end for millimeter-wave passive imaging in a 0.18-μm BiCMOS process is presented. The proposed system is comprised of a direct-detection front-end architecture employing a balanced LNA with an embedded Dicke switch, power detector, and baseband circuitry. The use of a balanced LNA with an embedded Dicke switch minimizes front-end noise figure, resulting in a great imaging resolution. The receiver chip achieves a measured responsivity of 20-43 MV/W with a front-end 3-dB bandwidth of 26 GHz, while consuming 200 mW. The calculated NETD of the SiGe receiver chip is 0.4 K with a 30 ms integration time. This work demonstrates the possibility of silicon-based system-on-chip solutions as lower cost alternatives to compound semiconductor multi-chip imaging modules.

A 94-GHz passive imaging receiver using a balanced LNA with embedded Dicke switch

A fully-integrated silicon-based 94-GHz direct-detection imaging receiver with on-chip Dicke switch and baseband circuitry is demonstrated. Fabricated in a 0.18-µm SiGe BiCMOS technology (fT/fMAX = 200 GHz), the receiver chip achieves a peak imager responsivity of 43 MV/W with a 3-dB bandwidth of 26 GHz. A balanced LNA topology with an embedded Dicke switch provides 30-dB gain and enables a temperature resolution of 0.3–0.4 K. The imager chip consumes 200 mW from a 1.8-V supply.

Design and Analysis of a W-band 9-Element Imaging Array Receiver Using Spatial-Overlapping Super-Pixels in Silicon

A W-band direct-detection-based receiver array is presented using a new concept of spatial-overlapping super-pixels for millimeter-wave imaging applications in an advanced 0.18 μm BiCMOS process. The use of spatial-overlapping super-pixels results in improved SNR at the pixel level through a reduction of spillover losses, partially correlated adjacent super-pixels, a 2×2 window averaging function in the RF domain, the ability to compensate for the systematic phase delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point, and the ability to compensate for mutual coupling effects among the array elements. The receiver chip achieves a measured peak coherent responsivity of 1,150 MV/W, an incoherent responsivity of 1,000 MV/W, a minimum NEP of 0.28 fW/Hz 1/2 and a front-end 3-dB bandwidth from 87-108 GHz, while consuming 225 mW per receiver element. The measured NETD of the SiGe receiver chip is 0.45 K with a 20 ms integration time.

A 93-to-113GHz BiCMOS 9-element imaging array receiver utilizing spatial-overlapping pixels with wideband phase and amplitude control

Benefiting from aggressive feature size scaling, silicon technologies have recently shown the capability of implementing W-band imaging receivers with an image resolution of 1.5mm and temperature resolutions of less than 0.5K [1-4]. This paper extends the capability of an imaging array receiver by improving image resolution using the novel concept of spatial-overlapping sub-arrays and enhancing image capture time using a phased-array within an imaging array receiver (RX). Specifically, the design and implementation of a BiCMOS 9-element array RX consisting of four 2×2 overlapping sub-arrays is presented. The RF-path-sharing between neighboring sub-arrays leads to a reduction in the chip area by 40% as compared to a conventional imaging array consisting of four 2×2 non-overlapping sub-arrays, while improving the RXs spatial resolution due to the higher sub-array density. Each 2×2 sub-array in this imaging array RX forms a pixel (Fig. 8.5.1).

Investigation of a Wideband BiCMOS Fully On-Chip

Design and implementation of a W-band on-chip bowtie-shaped slot antenna fabricated in 180-nm BiCMOS process is presented, and its performance and limitations are discussed. This antenna has a measured impedance bandwidth (S11 <; -10 dB) across the W-band frequency range and a very wide gain bandwidth, making it a candidate for wideband applications. The measured gain for this antenna is 0-1 dBi at 94 GHz. This letter also analyzes the influence of the RF probe to the on-chip antenna performance.

W

A 45GHz 64QAM system-on-chip (SoC) CMOS transmitter with digitally-assisted power amplifiers (DAPA) is presented. The SoC includes a 7M gate ASIC with 9b reconfigurable symbol mapping, 8X upsampling, 161tap pulse shape filtering, IQ imbalance correction and DAPA envelope/time estimation. The ASIC feeds two 10b IQ current-steering DACs and active IQ modulator. A unique transformer splitting up converter drives eight parallel combined DAPAs. The chip is packaged in aluminum housing with WR22 outputs. A 64QAM signal achieves 1.8% EVM with 33dBc ACPR at 45GHz. The data rate is 450Mbps and the integrated output power exceeds -10dBm.

-Band Bowtie Slot Antenna

The paper presents several feasible millimeter wave on-chip antenna designs suitable to be fabricated in CMOS technology without any additional process. The results are listed and compared with state-of-the-art designs in the literature. The difficulties in designing high efficiency antenna on CMOS chip are discussed.

A 45GHz CMOS transmitter SoC with digitally-assisted power amplifiers for 64QAM efficiency improvement

This paper presents the design and implementation of a W-band LNA. Fabricated in a 0.18-μm SiGe BiCMOS technology, the five-stage LNA achieves a peak power gain of 19 dB with a 3-dB bandwidth from 70–97 GHz and a minimum noise figure of 9 dB. The LNA exhibits more than 10-dB gain and input return loss <-12 dB across the entire W-band (75–110 GHz). The SiGe LNA is suitable for several W-band applications including 77/79-GHz automotive radars and passive imaging in the 80–110 GHz window.

Designs of fully on-chip antennas in (Bi)CMOS technology

This paper presents a W-band fully on-chip bowtie slot antenna over a grounded low resistivity silicon substrate fabricated in 180 nm BiCMOS process. The measured results show that the proposed antenna could provide a wide input bandwidth covering the whole W-band. The simulated gain at 90 GHz is -1 dBi when considering several realistic effects.

A W-band LNA in 0.18-μm SiGe BiCMOS

The first reported reconfigurable wideband mm-wave CMOS based beam forming network IC is demonstrated. The IC consists of two independent inputs and two correlated outputs. Each of the four RF paths has 2 bits amplitude control and 3 bits phase control, as well as a wideband amplifier to maintain RF signal power. The measured RMS amplitude and phase error is less than 0.4dB and 4° respectively. Amplifier power gating is added for low-power modes and calibration. An addressable shift register core (ASRC) to command the beam forming IC is included. The ASRC provides intelligent control of adjacent III-V based chips. The IC is 5mmX5mm and consumes 45mW of DC power.